Jump to content

Intel corporation (20250103547). SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

From WikiPatents

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Organization Name

intel corporation

Inventor(s)

Prasoonkumar Surti of Folsom CA US

Subramaniam Maiyuran of Gold River CA US

Valentin Andrei of San Jose CA US

Abhishek Appu of El Dorado Hills CA US

Varghese George of Folsom CA US

Altug Koker of El Dorado Hills CA US

Mike Macpherson of Portland OR US

Elmoustapha Ould-ahmed-vall of Chandler AZ US

Vasanth Ranganathan of El Dorado Hills CA US

Joydeep Ray of Folsom CA US

Lakshminarayanan Striramassarma of Folsom CA US

SungYe Kim of Folsom CA US

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

This abstract first appeared for US patent application 20250103547 titled 'SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Original Abstract Submitted

embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. one embodiment provides techniques to use decompression information when performing sparse compute operations. one embodiment enables the disaggregation of special function compute arrays via a shared reg file. one embodiment enables packed data compress and expand operations on a gpgpu. one embodiment provides techniques to exploit block sparsity within the cache hierarchy of a gpgpu.

Cookies help us deliver our services. By using our services, you agree to our use of cookies.