Texas Instruments Incorporated patent applications on January 30th, 2025
Patent Applications by Texas Instruments Incorporated on January 30th, 2025
Texas Instruments Incorporated: 25 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H02M3/158 (3), G06F12/0811 (3), G06F11/10 (3), G06F9/30 (3), G06F9/48 (2) H02M1/088 (2), G01K7/425 (1), H02H3/08 (1), H01L29/7816 (1), H01L29/7786 (1)
With keywords such as: control, coupled, device, circuit, memory, signal, layer, input, output, and configured in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
20250035492. TEMPERATURE-BASED TAMPER DETECTION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Anand Kumar G of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G01K7/42, G01K1/022, G06F12/16
CPC Code(s): G01K7/425
Abstract: a device includes first and second circuits. the first circuit includes a temperature sensor to measure a device temperature. the second circuit operates to send an enable signal to the first circuit to cause the temperature sensor to measure the device temperature; and, in response to not receiving at least one of a ready signal and the device temperature from the first circuit within a set amount of time, output a tamper event signal and a timeout event signal, and disable a valid data signal.
Inventor(s): Karthik SUBBURAJ of Bangalore (IN) for texas instruments incorporated, Sandeep RAO of Bangalore (IN) for texas instruments incorporated, Karthik RAMASUBRAMANIAN of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01S7/40, G01S7/35, G01S13/931
CPC Code(s): G01S7/4021
Abstract: in some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (lo) frequency of the first device by a target offset and reflected off a target. the method also includes determining an intermediate frequency (if) of the radar signal based on the transmission frequency and the lo frequency. the method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.
Inventor(s): Tomas MOTOS of Hamar (NO) for texas instruments incorporated, Espen WIUM of Oslo (NO) for texas instruments incorporated
IPC Code(s): G01S13/84, B60R25/24
CPC Code(s): G01S13/84
Abstract: systems and methods of measuring distance between two wireless devices by combining phase shift and time-of-flight measurements. a first wireless devices sends a first packet to the second wireless device. after receiving the first packet, the second wireless device sending to the first wireless device a second packet. after sending the second packet, the second wireless device sends a first continuous wave signal to the first wireless device. after receiving the first continuous wave signal, the first wireless device sends to the second wireless device a second continuous wave signal. the first wireless device then calculates a time-of-flight measurement based on a time between the first wireless device sending the first packet and receiving the second packet, and calculates a second measurement based on a phase shift of the first continuous wave signal and the second continuous wave signal, and combines the two measurements.
Inventor(s): Adam Joseph FRUEHLING of Garland TX (US) for texas instruments incorporated, James Norman HALL of Parker TX (US) for texas instruments incorporated
IPC Code(s): G02B26/08, G02B26/06, H02N1/00
CPC Code(s): G02B26/0841
Abstract: a microelectromechanical systems (mems) device includes a base plate including a first electrode and a second electrode and a top layer. the mems device also includes a perforated hinge plate supporting the top layer. the perforated hinge plate includes first and second flexural arms permitting the perforated hinge plate and the top layer to move relative to the base plate. the perforated hinge plate has a first perforation that includes the first electrode and has a footprint that is larger than a footprint of the first electrode, and the perforated hinge plate has a second perforation that includes the second electrode and has a footprint that is larger than a footprint of the second electrode. additionally, the mems device includes a first support post to which the first flexural arm is connected and a second support post to which the second flexural arm is connected.
Inventor(s): Sira Parasurama Rao of Richmond TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06, G06F8/654, G06F8/656
CPC Code(s): G06F3/0604
Abstract: in described examples, a flash memory bank includes application and bootloader portions. the application portion stores first instructions for performing an interrupt service routine (isr). the bootloader portion stores second instructions for: causing the flash memory bank to receive new first instructions for performing the isr and write the new first instructions to replace old first instructions, and executing the new first instructions. the new first instructions execute the following steps in order. first, while maintaining an interrupt response, initializing variables specified by the new first instructions and not specified by the old first instructions, and not changing variables specified by the old first instructions. second, after determining there is no interrupt response in process, disabling the interrupt response and proceeding to a third step. third, initializing a stack, updating an interrupt vector, and updating a function pointer. fourth, re-enabling the interrupt response.
20250036315. FLASH MEMORY ACCESS SCHEDULING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Sriramakrishnan Govindarajan of Bangalore (IN) for texas instruments incorporated, Vignesh Raghavendra of Bangalore (IN) for texas instruments incorporated, Mihir Mody of Bangalore (IN) for texas instruments incorporated, Mohammad Asif Farooqui of Bangalore (IN) for texas instruments incorporated, Shailesh Ghotgalkar of Bangalore (IN) for texas instruments incorporated, Sai Rajaraman of Frisco TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. in an example embodiment, a system is provided. the system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. the memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. the processing circuitry executes the set of instructions.
Inventor(s): Son Hung Tran of Murphy TX (US) for texas instruments incorporated, Shyam Jagannathan of Bangalore (IN) for texas instruments incorporated, Timothy David Anderson of University Park TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/32, G06F9/345, G06F9/38, G06F11/00, G06F11/10, G06F12/0811, G06F12/0875, G06F12/0897, G06F15/80, G06F17/16
CPC Code(s): G06F9/3016
Abstract: software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. the stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. a stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. when the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.
Inventor(s): David Matthew THOMPSON of Dallas TX (US) for texas instruments incorporated, Abhijeet Ashok CHACHAD of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F11/10, G06F9/30, G06F9/38, G06F9/448, G06F9/46, G06F9/48, G06F9/52, G06F12/0811, G06F12/0815, G06F12/0879, G06F12/0888, G06F12/0895, G06F12/128, G06F13/16, H03M13/15
CPC Code(s): G06F11/106
Abstract: a device includes memory blocks; connections respectively coupled to the memory blocks; and control logic coupled to the memory blocks. the control logic is operable to control performance of error-related transactions on the memory blocks via the connections. such control may include causing a first error-related transaction to be performed on a first memory block of the memory blocks during a first time period, causing a second error-related transaction to be performed on a second memory block of the memory blocks during a second time period, and causing a transaction that is not an error-related transaction to be performed on at least one of the memory blocks, except the first memory block, during performance of one or both of the first error-related transaction and the second error-related transaction.
Inventor(s): Jason Lynn PECK of Houston TX (US) for texas instruments incorporated, Gary A. COOPER of Oakmont PA (US) for texas instruments incorporated, Markus KOESLER of Landshut (DE) for texas instruments incorporated
IPC Code(s): G06F11/36, G06F9/48
CPC Code(s): G06F11/3656
Abstract: a method includes executing, by a processor, a first code section having a first priority; encountering, by the processor, during the executing of the first code section, a breakpoint; receiving, by the processor, while at the breakpoint, an interrupt associated with a second code section, the interrupt having a second priority that is higher than the first priority; servicing, by the processor, the interrupt including executing the second code section; receiving a debug access request associated with the breakpoint during the servicing of the interrupt; blocking servicing of the debug access request until servicing of the interrupt is completed; and servicing, by the processor, the debug access request after completing service of the interrupt.
Inventor(s): Naveen Bhoria of Plano TX (US) for texas instruments incorporated, Timothy David Anderson of University Park TX (US) for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture are disclosed for read-modify-write support in multi-banked data ram cache for bank arbitration. an example data cache system includes a store queue including a plurality of bank queues including a first bank queue having a write and read port configured to receive a respective write and read operation, storage coupled to the store queue including a plurality of data banks including a first data bank having a first port configured to receive the write or the read operation, first through third multiplexers, and bank arbitration logic including first arbiters including a first arbiter and second arbiters including a second arbiter, the first arbiter coupled to the second arbiter, the second and third multiplexers, the second arbiter coupled to the first multiplexer.
Inventor(s): Robin Osa HOEL of Oslo (NO) for texas instruments incorporated, Aniruddha PERIYAPATNA NAGENDRA of Bangalore (IN) for texas instruments incorporated, Prithvi Shankar YEYYADI ANANTHA of Bangalore (IN) for texas instruments incorporated, Shobhit SINGHAL of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G11C11/413
CPC Code(s): G11C11/413
Abstract: in an example, a system includes an sram configured to store a plurality of access control rules, where each rule is stored in a separate row. the sram is configured to store a plurality of context entries, where each context entry is stored in a separate row. the system includes a controller configured to receive a request for an access control rule for a memory location from a first context. the controller is configured to search one or more access control rules for the first context, where access control rules for the first context are stored in a binary tree format. the controller is configured to, responsive to finding the access control rule for the memory location, return the access control rule to the first context. the controller is configured to, responsive to not finding the access control rule, return a null notification to the first context.
Inventor(s): Kengo Aoya of Beppu-shi (JP) for texas instruments incorporated, Masamitsu Matsuura of Beppu-shi (JP) for texas instruments incorporated, Daiki Komatsu of Beppu-shi (JP) for texas instruments incorporated
IPC Code(s): H01L21/48, H01L21/56, H01L23/31, H01L23/495
CPC Code(s): H01L21/4842
Abstract: a semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. the relief recess has a relief width greater than a thickness of the leads under the relief recess. top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. in both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. a majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. the semiconductor package is singulated by sawing through the leads.
20250038077. ELECTRONIC DEVICE WITH LEAD LOCK_simplified_abstract_(texas instruments incorporated)
Inventor(s): CHU-YUN LO of Taipei City (TW) for texas instruments incorporated, MEGAN CHANG of Taipei City (TW) for texas instruments incorporated, YUH-HARNG CHIEN of New Taipei City (TW) for texas instruments incorporated
IPC Code(s): H01L23/495
CPC Code(s): H01L23/49524
Abstract: an electronic device includes a leadframe having a die pad, inner leads, and outer leads. the die is attached to the die pad, where the die includes an active side. lead locks are disposed adjacent to the inner leads. the lead locks include a side support disposed on each side of the inner leads and an opening defined between each side support and the inner leads. wire bonds are attached from the active side of the die to the inner leads and a mold compound is formed to encapsulate the die, the inner leads, the lead locks, and the wire bonds.
Inventor(s): Prateek Pandey of Bangalore (IN) for texas instruments incorporated, Koshal Sharma of Bangalore (IN) for texas instruments incorporated, Aalok Dyuti Saha of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02H3/08
CPC Code(s): H02H3/08
Abstract: an apparatus includes a first comparator having first and second inputs, a first control input, an output, and a supply voltage terminal. a second comparator has first and second inputs, a second control input, and an output. the second comparator's first input is coupled to the first input of the first comparator. the second comparator's second input is coupled to the first comparator's second input. a switchover logic circuit has an input, a first output, a second output, and a third output. the input of the switchover logic circuit is coupled to the first inputs of the first and second comparators. the first output of the switchover logic circuit is coupled to the supply voltage terminal of the first comparator. the second output of the switchover logic circuit is coupled to the first control input. the third output of the switchover logic circuit is coupled to the second control input.
Inventor(s): Isaac Cohen of Dix Hills NY (US) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M1/32, H02M1/42, H02M3/158, H02M7/217
CPC Code(s): H02M1/0009
Abstract: in an example, a current estimating circuit includes a current estimating resistor coupled in series with a current estimating capacitor. the current estimating resistor and the current estimating capacitor are configured to provide a voltage across the current estimating capacitor during a first portion of a switching cycle, in which the voltage across the current estimating capacitor is proportional to an inductor current that flows through an inductor. the current estimating circuit includes a sense resistor configured to provide a sensed voltage across the sense resistor during a second portion of the switching cycle. the current estimating circuit includes a switch configured to apply the sensed voltage to the current estimating capacitor to provide the voltage across the current estimating capacitor during the second portion of the switching cycle.
Inventor(s): Janne PAHKALA of Oulu (FI) for texas instruments incorporated, Ari VAANANEN of Oulu (FI) for texas instruments incorporated
IPC Code(s): H02M1/088, H02M1/00, H02M1/14, H02M3/158
CPC Code(s): H02M1/088
Abstract: a circuit includes a controller. the controller includes: a first control circuit; a second control circuit; a detection circuit; mode control logic; and driver circuitry. a first input of the mode control logic is coupled to an output of the first control circuit. a second input of the mode control logic coupled to an output of the second control circuit. a third input of the mode control logic is coupled to an output of the detection circuit. a first input of the driver circuitry is coupled to a first output of the mode control logic. a second input of the driver circuitry is coupled to a second output of the mode control logic.
20250038645. ACTIVE VOLTAGE CLAMP CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Taisuke Kazama of PLANO TX (US) for texas instruments incorporated, Mustapha El-Markhi of RICHARDSON TX (US) for texas instruments incorporated, Avadhut Junnarkar of MCKINNEY TX (US) for texas instruments incorporated, Indumini W. Ranmuthu of PLANO TX (US) for texas instruments incorporated
IPC Code(s): H02M1/088, H02M3/158
CPC Code(s): H02M1/088
Abstract: described embodiments include a gate drive circuit with a first transistor coupled between an input voltage terminal and a switching terminal, and having a first control terminal. a second transistor is coupled between the switching terminal and ground, and has a second control terminal. a first driver circuit has a first driver output coupled to the first control terminal, a first positive supply input coupled to a bootstrap voltage terminal, and a first negative supply input coupled to the switching terminal. a second driver circuit has a second driver output coupled to the second control terminal, a second positive supply input coupled to a driver supply, and a first negative supply input coupled to ground. an active clamp circuit is coupled between the driver supply and ground, and prevents a voltage between the driver supply and ground from exceeding a threshold voltage.
Inventor(s): Animesh PAUL of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03L7/087, H03L7/093, H03L7/099
CPC Code(s): H03L7/087
Abstract: in an example, a phase-locked loop (pll) circuit includes an oscillator, a frequency search circuit, and an analog control loop. the oscillator is configured to provide a clock signal. the frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. the analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.
Inventor(s): Sriram Murali of Bangalore (IN) for texas instruments incorporated, Aswath VS of Kannur (IN) for texas instruments incorporated, Sreenath Narayanan Potty of Bangalore (IN) for texas instruments incorporated, Raju K. Chaudhari of Bangalore (IN) for texas instruments incorporated, Kapil Kumar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04L27/26, H04B1/04
CPC Code(s): H04L27/2614
Abstract: an example apparatus to reduce crests in an input signal includes: memory; and programmable circuitry configured to: store a first copy and a second copy of a normalized window waveform in the memory, the first copy of the normalized window waveform including more data points than the second copy of the normalized window waveform; use the second copy of the normalized window waveform to generate a weight corresponding to a peak in the input signal; use the weight and the first copy of the normalized window waveform to generate an output waveform; generate a peak limiting waveform responsive to the output waveform; and combine the peak limiting waveform with the input signal to reduce an amplitude of the peak.
20250039417. CONTEXT AND BYPASS CODING VIDEO_simplified_abstract_(texas instruments incorporated)
Inventor(s): Madhukar Budagavi of Plano TX (US) for texas instruments incorporated, Mehmet U. Demircin of Dallas TX (US) for texas instruments incorporated, Vivienne Sze of Cambridge MA (US) for texas instruments incorporated
IPC Code(s): H04N19/436, H04N19/13, H04N19/139, H04N19/176, H04N19/46, H04N19/70, H04N19/91
CPC Code(s): H04N19/436
Abstract: a method and apparatus for parallel context processing for example for high coding efficient entropy coding in hevc. the method comprising retrieving syntax element relating to a block of an image, grouping at least two bins belonging to similar context based on the syntax element, and coding the grouped bins in parallel.
Inventor(s): Ariton Xhafa of Plano TX (US) for texas instruments incorporated, Yaron Alpert of Hod-Hasharon (IL) for texas instruments incorporated
IPC Code(s): H04W72/12, H04W72/50, H04W72/566
CPC Code(s): H04W72/12
Abstract: an example apparatus includes: interface circuitry; and programmable circuitry configured to: transmit a first schedule to a set of battery modules, the first schedule to assign transmission slots to one or more of the set of battery modules for a first communication period; create a second schedule different from the first schedule; and transmit the second schedule to the set of battery modules, the second schedule to assign transmission slots to one or more of the set of battery modules for a second communication period.
Inventor(s): Arvind K. Raghu of Plano TX (US) for texas instruments incorporated, Ariton E. Xhafa of Plano TX (US) for texas instruments incorporated, Ramanuja Vedantham of Allen TX (US) for texas instruments incorporated, Xiaolin Lu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W72/23, H04W72/1273
CPC Code(s): H04W72/23
Abstract: a network includes a parent node and at least one child node configured to communicate with the parent node via a wireless network protocol. the parent node includes a broadcast coordinator to transmit a broadcast message from the parent node to the child node at predetermined time intervals according to the wireless network protocol. a scheduler generates a scheduling packet that is communicated in the broadcast message. the scheduling packet includes a data field to instruct each child node to activate and receive data communicated from the parent node in a prescribed time slot following the broadcast message that is defined by the scheduling packet.
Inventor(s): Dong Seup Lee of McKinney TX (US) for texas instruments incorporated
IPC Code(s): H01L29/778, H01L23/31, H01L29/20, H01L29/66
CPC Code(s): H01L29/7786
Abstract: the present disclosure generally relates to a semiconductor device having a doped region underlying a gate layer and in a barrier layer. in an example, a semiconductor device includes a channel layer, a barrier layer, and a gate layer. the channel layer is over a semiconductor substrate, and the barrier layer is over the channel layer. the gate layer is over the barrier layer, and the gate layer is doped with a dopant. a first region in the barrier layer overlies a channel region in the channel layer and underlies the gate layer. the first region has a first concentration of the dopant. a second region in the barrier layer is laterally disposed from the first region. the second region has a second concentration of the dopant that is less than the first concentration.
Inventor(s): Pushpa Mahalingam of Richardson TX (US) for texas instruments incorporated, Alexei Sadovnikov of Sunnyvale CA (US) for texas instruments incorporated, Nick Dunteman of Draper UT (US) for texas instruments incorporated, Ryan Rust of Lehi UT (US) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L29/06, H01L29/08, H01L29/423, H01L29/66
CPC Code(s): H01L29/7816
Abstract: semiconductor devices including a high-k field relief dielectric structure are described. the microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a locos silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. a drain drift trench formed in a trench left after removal of silicon dioxide in a locos region provides improved trench depth uniformity.
Inventor(s): Qhalid RS Fareed of Plano TX (US) for texas instruments incorporated, Dong Seup Lee of Mckinney TX (US) for texas instruments incorporated, Nicholas S. Dellas of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L29/15, H01L21/02
CPC Code(s): H01L29/151
Abstract: fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. in one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.
Texas Instruments Incorporated patent applications on January 30th, 2025
- Texas Instruments Incorporated
- G01K7/42
- G01K1/022
- G06F12/16
- CPC G01K7/425
- Texas instruments incorporated
- G01S7/40
- G01S7/35
- G01S13/931
- CPC G01S7/4021
- G01S13/84
- B60R25/24
- CPC G01S13/84
- G02B26/08
- G02B26/06
- H02N1/00
- CPC G02B26/0841
- G06F3/06
- G06F8/654
- G06F8/656
- CPC G06F3/0604
- CPC G06F3/0659
- G06F9/30
- G06F9/32
- G06F9/345
- G06F9/38
- G06F11/00
- G06F11/10
- G06F12/0811
- G06F12/0875
- G06F12/0897
- G06F15/80
- G06F17/16
- CPC G06F9/3016
- G06F9/448
- G06F9/46
- G06F9/48
- G06F9/52
- G06F12/0815
- G06F12/0879
- G06F12/0888
- G06F12/0895
- G06F12/128
- G06F13/16
- H03M13/15
- CPC G06F11/106
- G06F11/36
- CPC G06F11/3656
- G06F9/54
- G06F12/02
- G06F12/0802
- G06F12/0804
- G06F12/0806
- G06F12/0817
- G06F12/0853
- G06F12/0855
- G06F12/0864
- G06F12/0884
- G06F12/0891
- G06F12/12
- G06F12/121
- G06F12/126
- G06F12/127
- G11C5/06
- G11C7/10
- G11C7/22
- G11C29/42
- G11C29/44
- CPC G06F12/128
- G11C11/413
- CPC G11C11/413
- H01L21/48
- H01L21/56
- H01L23/31
- H01L23/495
- CPC H01L21/4842
- CPC H01L23/49524
- H02H3/08
- CPC H02H3/08
- H02M1/00
- H02M1/32
- H02M1/42
- H02M3/158
- H02M7/217
- CPC H02M1/0009
- H02M1/088
- H02M1/14
- CPC H02M1/088
- H03L7/087
- H03L7/093
- H03L7/099
- CPC H03L7/087
- H04L27/26
- H04B1/04
- CPC H04L27/2614
- H04N19/436
- H04N19/13
- H04N19/139
- H04N19/176
- H04N19/46
- H04N19/70
- H04N19/91
- CPC H04N19/436
- H04W72/12
- H04W72/50
- H04W72/566
- CPC H04W72/12
- H04W72/23
- H04W72/1273
- CPC H04W72/23
- H01L29/778
- H01L29/20
- H01L29/66
- CPC H01L29/7786
- H01L29/78
- H01L29/06
- H01L29/08
- H01L29/423
- CPC H01L29/7816
- H01L29/15
- H01L21/02
- CPC H01L29/151