18374951. Speculative Cache Invalidation for Processing-in-Memory Instructions (Advanced Micro Devices, Inc.)
Speculative Cache Invalidation for Processing-in-Memory Instructions
Organization Name
Inventor(s)
Travis Henry Boraten of Austin TX US
Jagadish B. Kotra of Austin TX US
David Andrew Werner of Austin TX US
Speculative Cache Invalidation for Processing-in-Memory Instructions
This abstract first appeared for US patent application 18374951 titled 'Speculative Cache Invalidation for Processing-in-Memory Instructions
Original Abstract Submitted
Speculative cache invalidation techniques for processing-in-memory instructions are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. The system employs speculative evaluation logic to identify whether the data associated with the processing-in-memory request is stored in the cache system before the processing-in-memory request is transmitted to the cache coherence controller. If the data is stored in the cache system, the cache system locally invalidates or flushes the data to avoid stalling the processing-in-memory request during a cache directory lookup.
