INTEL CORPORATION patent applications on April 3rd, 2025
Patent Applications by INTEL CORPORATION on April 3rd, 2025
INTEL CORPORATION: 137 patent applications
INTEL CORPORATION has applied for patents in the areas of H01L23/00 (38), H01L25/065 (23), H01L29/06 (20), H01L23/538 (20), H01L23/498 (18) H01L24/08 (4), H01L23/562 (3), H10D84/85 (3), H01L25/0652 (3), H01L25/0655 (3)
With keywords such as: substrate, structure, die, layer, circuit, integrated, material, device, structures, and surface in patent application abstracts.
Patent Applications by INTEL CORPORATION
Inventor(s): Andrey Vyatskikh of Hillsboro OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Jeffery D. Bielefeld of Forest Grove OR US for intel corporation, Grant M. Kloster of Lake Oswego OR US for intel corporation, Carlos Bedoya Arroyave of Portland OR US for intel corporation, Golsa Naderi of Portland OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation
IPC Code(s): B23K26/40, B23K26/53, B23K101/40, B23K103/00
CPC Code(s): B23K26/40
Abstract: an embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (ic) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.
Inventor(s): Wenhao Li of Chandler AZ US for intel corporation, Veronica Strong of Hillsboro OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR US for intel corporation
IPC Code(s): C08F20/18, C08F22/10, C09J133/10
CPC Code(s): C08F20/18
Abstract: hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. one or both of an integrated circuit (ic) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. the hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the ic die to self-align. a hybrid bond is formed by evaporating the droplet and a subsequent anneal. the cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.
Inventor(s): Vanessa POGUE of Tucson AZ US for intel corporation, Hari MAHALINGAM of San Jose CA US for intel corporation, Joshua JOHNSON of Chandler AZ US for intel corporation, Jordan DAVIS of Santa Clara CA US for intel corporation, Ranjeet KUMAR of Milpitas CA US for intel corporation, Yen-Jung CHEN of San Jose CA US for intel corporation, Andrew DEVINE of Santa Clara CA US for intel corporation, Mahtab HAKAMI of Santa Clara CA US for intel corporation
IPC Code(s): G01L1/24
CPC Code(s): G01L1/24
Abstract: the present disclosure is directed to testing vehicles for optical devices and other semiconductor devices that have insitu sensor units for measuring localized strains, and methods for their use. in an aspect, the optical device may include a photonic integrated circuit device having several components including a laser, an optical amplifier, a waveguides, a modulator, a demodulator, and photodetectors. in another aspect, the sensor unit may include a micro-ring resonator strain sensor, an input grating coupler and an output grating coupler that are coupled to the micro-ring resonator strain sensor, for which the input grating coupler is coupled to a light source and the output grating coupler is coupled to an optical power meter. in yet another aspect, the sensor unit may include a temperature calibration unit having a heater and a temperature diode.
Inventor(s): Gregorio R. Murtagian of Phoenix AZ US for intel corporation
IPC Code(s): G01R31/28, G01K1/22, G01K1/26
CPC Code(s): G01R31/287
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed that improve thermal tests of integrated circuit devices. an example apparatus includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a condition of a fluid to be dispensed by a pneumatic nozzle, the condition of the fluid including a temperature of the fluid; determine a ratio of a first liquid, a second liquid, and a superheated vapor that combine to result in the condition of the fluid; and cause the first liquid, the second liquid, and the superheated vapor to be provided to the pneumatic nozzle in proportions defined by the ratio.
Inventor(s): Rakesh KANDULA of Bangalore IN for intel corporation, Sankaran M. MENON of Austin TX US for intel corporation, Rolf KUEHNIS of Portland OR US for intel corporation
IPC Code(s): G01R31/319, G01R31/28, G01R31/317, G01R31/3185
CPC Code(s): G01R31/31917
Abstract: methods, apparatus, and computer programs are disclosed to detect computing system hardware defects using a portable storage device. in one embodiment, a method includes accessing a portable storage device to obtain an identifier and a set of test patterns to test a set of circuits of a computing system, the identifier to map to the set of test patterns. the method further includes determining that the set of test patterns is to be executed on the computing system based on the identifier to be obtained from accessing the portable storage device. responsive to the determination, and executing the set of test patterns loaded from the portable storage device on the set of circuits of the computing system to detect one or more hardware defects of the set of circuits.
20250110209. RADAR APPARATUS, SYSTEM, AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Merav Sicron of Kfar-Saba IL for intel corporation, Ofer Gueta of Ganei-Tikva IL for intel corporation, Kfir Mandel of Ramat Gan IL for intel corporation, Ophir Shabtay of Tsofit IL for intel corporation, Adi Panzer of Tel Aviv IL for intel corporation, Ziv Barak of Rishon-LeZion IL for intel corporation
IPC Code(s): G01S7/41, G01S7/35, G01S13/931
CPC Code(s): G01S7/411
Abstract: for example, a radar radio head (rh) may be configured to determine range-doppler (rd) information corresponding to a plurality of rd bins based on digital radar receive (rx) signals representing radar radio frequency (rf) rx signals received by one or more rx antennas; to detect one or more detected rd bins based on the rd information; to provide filtered rd information including rd information corresponding to the one or more detected rd bins and excluding rd information of one or more excluded rd bins, which are not included in the one or more detected rd bins; and to send the filtered rd information to another processor via a communication interconnect.
Inventor(s): Chia-Pin Chiu of Tempe AZ US for intel corporation, Kaveh Hosseini of Livermore CA US for intel corporation
IPC Code(s): G02B6/12
CPC Code(s): G02B6/12002
Abstract: the substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. the multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (pic) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second pic die. the integrated circuit component further includes a first intermediate waveguide optically coupling a first pic waveguide of the first pic die to a first substrate waveguide in the substrate, and a second intermediate waveguide optically coupling a second pic waveguide of the second pic die to a second substrate waveguide in the substrate. the integrated circuit component may further include a third intermediate waveguide optically coupling the first pic die to the second pic die.
Inventor(s): Sufi R. Ahmed of Chandler AZ US for intel corporation, Darren Vance of Gilbert AZ US for intel corporation, Sang Yup Kim of Sunnyvale CA US for intel corporation, Anthony Traynor of Livingston GB for intel corporation, Eric J. M. Moret of Beaverton OR US for intel corporation
IPC Code(s): G02B6/36
CPC Code(s): G02B6/3652
Abstract: architectures and methods for attaching photonic integrated circuits (pics) to optical connectors. the architectures are characterized by (1) a cavity at a specific location with respect to a trench alongside an optical facet of the pic die, (2) index matching epoxy (ime) in the trench and in the cavity, and (3) the use of a snap cure adhesive between the pic and the optical connector.
20250110289. OPTICAL CONNECTOR FERRULE_simplified_abstract_(intel corporation)
Inventor(s): Benjamin T. Duong of Phoenix AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Sandeep Gaan of Chandler AZ US for intel corporation, Donald Hammon of Fox Island WA US for intel corporation, Wesley B. Morgan of Lake Oswego OR US for intel corporation
IPC Code(s): G02B6/38
CPC Code(s): G02B6/3881
Abstract: a ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. the ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. the ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.
Inventor(s): Chia-Pin Chiu of Tempe AZ US for intel corporation, Kaveh Hosseini of Livermore CA US for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4226
Abstract: technologies for an optical interposer with actuator beams are disclosed. in one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (pic) die. the optical interposer includes actuator beams and waveguides embedded in the actuator beams. an electrical trace is disposed on the actuator beams. in use, current can pass through the electrical trace, expanding the trace through thermal expansion. the trace expands more than the actuator beam underneath it, causing the actuator beam and the waveguides to be deflected. in this manner, the waveguides in the optical interposer can be positioned to align to waveguides in the pic die.
20250110295. POLYETHYLENE OXIDE-BASED OPTICAL ADHESIVE_simplified_abstract_(intel corporation)
Inventor(s): Ziyin Lin of Chandler AZ US for intel corporation, Saikumar Jayaraman of Chandler AZ US for intel corporation, Yiqun Bai of Chandler AZ US for intel corporation, Fan Fan of Chandler AZ US for intel corporation, Dingying Xu of Chandler AZ US for intel corporation
IPC Code(s): G02B6/42, C09J171/02
CPC Code(s): G02B6/4239
Abstract: a set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. the set of optical fibers are adhered within the grooves using a polyethylene oxide (peo)-based adhesive. the peo-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
Inventor(s): Saeed Fathololoumi of Los Gatos CA US for intel corporation, Reece Andrew DeFrees of Rio Rancho NM US for intel corporation, Kelly Christopher Magruder of Albuquerque NM US for intel corporation, Harel Frish of Albuquerque NM US for intel corporation, John M. Heck of Berkeley CA US for intel corporation, Ling Liao of Fremont CA US for intel corporation, David Chak Wang Hui of Santa Clara CA US for intel corporation, Sushrutha Reddy Gujjula of Chandler AZ US for intel corporation
IPC Code(s): G02B6/42, H01L23/00, H01L23/367, H01L25/16, H01L25/18
CPC Code(s): G02B6/4274
Abstract: technologies for thermal plugs in photonic integrated circuit (pic) dies are disclosed. in an illustrative embodiment, several thermal plugs extend from contact pads in a pic die, through a dielectric layer, to a waveguide layer. the thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the pic die. the pic die may be mounted on an electronic integrated circuit (eic) die in an integrated circuit component. the pic die can transfer heat from the eic die, through the pic die, and to another component such as an integrated heat spreader, lowering the temperature of the eic die. the thermal plugs can increase the heat transfer through the pic die.
20250110408. SWITCHABLE UNDERLAYERS FOR EUV LITHOGRAPHY_simplified_abstract_(intel corporation)
Inventor(s): Robert JORDAN of Portland OR US for intel corporation, Brandon HOLYBEE of Portland OR US for intel corporation, James BLACKWELL of Portland OR US for intel corporation, Blake BLUESTEIN of Hillsboro OR US for intel corporation, Eric MATTSON of Portland OR US for intel corporation, Marie KRYSAK of Portland OR US for intel corporation, Nicole GUZMAN of Newberg OR US for intel corporation, Shane HARLSON of Beaverton OR US for intel corporation, Eungnak HAN of Portland OR US for intel corporation, Florian GSTREIN of Portland OR US for intel corporation
IPC Code(s): G03F7/11, G03F7/20, G03F7/38
CPC Code(s): G03F7/11
Abstract: provided are methods and compounds for using an adhesively switchable underlayer beneath a photoresist in a lithographic process for making a semiconductor wafer.
Inventor(s): Leobardo Emmanuel CAMPOS MACIAS of Guadalajara MX for intel corporation, Rafael DE LA GUARDIA GONZALEZ of Teuchitlan MX for intel corporation, David GOMEZ GUTIERREZ of Tlaquepaque MX for intel corporation, David GONZALEZ AGUIRRE of Portland OR US for intel corporation, Julio ZAMORA ESQUIVEL of West Sacramento CA US for intel corporation
IPC Code(s): G05D1/02, G06T15/08, G06T17/00, G06V20/50, G06V20/70
CPC Code(s): G05D1/0274
Abstract: disclosed herein are devices, systems, and methods for representing a workspace of a robot. the system includes a sensor configured to capture an image of the workspace. the system also includes a processor in communication with the sensor. the processor is configured to convert the image into a point cloud representation of the workspace. the processor is also configured to determine, for at least one point in the point cloud representation, a hash code that relates a task state to a volumetric space associated with the at least one point. the processor is also configured to determine a motion plan for the robot within the workspace based on the hash code and to cause the robot to execute the motion plan.
Inventor(s): Angad Hiteshbhai Shah of Bangalore IN for intel corporation, Harithaa Varshini V of Bangalore IN for intel corporation, Uma Maheswari Trichy Sundaram of Chennai IN for intel corporation, Subhojit Saha of Bengaluru IN for intel corporation, Ashwin Sesha Srinivasan of Coimbatore IN for intel corporation, Sriram S of Kumbakonam IN for intel corporation, Ravi Sri Himaja of Bangalore IN for intel corporation
IPC Code(s): G06F1/324, G06F1/3234
CPC Code(s): G06F1/324
Abstract: an example apparatus includes memory; machine-readable instructions; and at least one programmable circuit to at least one of execute or instantiate the machine-readable instructions to at least adjust a frequency of a clock signal of the memory based on workload demands of a processor circuit.
Inventor(s): Jorge Eduardo Parra Osorio of El Dorado Hills CA US for intel corporation, Fangwen Fu of Folsom CA US for intel corporation, Guei-Yuan Lueh of San Jose CA US for intel corporation, Jiasheng Chen of El Dorado Hills CA US for intel corporation, Naveen K. Mellempudi of Bangalore IN for intel corporation, Kevin Hurd of Flagler Beach FL US for intel corporation, Alexandre Hadj-Chaib of Kings Langley GB for intel corporation, Elliot Taylor of London GB for intel corporation, Marius Cornea-Hasegan of Hillsborro OR US for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06T15/00
CPC Code(s): G06F9/30025
Abstract: an apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. the apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide input data for an input operand of the conversion operation indicated by the decoded instruction; and conversion circuitry to execute the decoded instruction to perform the conversion operation to convert the input operand to an output operand in accordance with the 8-bit floating point format operand, the conversion circuitry comprising hardware circuitry to rescale, normalize, and convert the input operand to the output operand.
Inventor(s): Eran SHIFER of Tel Aviv IL for intel corporation, Mostafa HAGOG of Kaukab IL for intel corporation, Eliyahu TURIEL of Shimshit IL for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F15/80
CPC Code(s): G06F9/30076
Abstract: an apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. the shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. the call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. other apparatus, methods, and systems are also disclosed.
20250110739. INSTRUCTION BLOCK BASED PERFORMANCE MONITORING_simplified_abstract_(intel corporation)
Inventor(s): Kshitij Arun Doshi of Tempe AZ US for intel corporation, Rahul Khanna of Portland OR US for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30145
Abstract: techniques for block based performance monitoring are described. in an embodiment, an apparatus includes execution hardware to execute a plurality of instructions; and block-based sampling hardware. the block-based sampling hardware is to identify, based on a first branch instruction of the plurality of instructions and a second branch instruction of the plurality of instructions, a block of instructions; and to collect, during execution of the block of instructions, performance information.
Inventor(s): Jorge Eduardo Parra Osorio of El Dorado Hills CA US for intel corporation, Fangwen Fu of Folsom CA US for intel corporation, Guei-Yuan Lueh of San Jose CA US for intel corporation, Hong Jiang of Los Altos CA US for intel corporation, Jiasheng Chen of El Dorado Hills CA US for intel corporation, Naveen K. Mellempudi of Bangalore IN for intel corporation, Kevin Hurd of Flagler Beach FL US for intel corporation, Chunhui Mei of San Diego CA US for intel corporation, Alexandre Hadj-Chaib of Kings Langley GB for intel corporation, Elliot Taylor of London GB for intel corporation, Shuai Mu of San Diego CA US for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/3016
Abstract: an apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and circuitry to execute the decoded instruction to perform 32-way dot-product using 8-bit wide dot-product layers, each 8-bit wide dot-product layer comprises one or more sets of interconnected multipliers, shifters, and adders, wherein each set of multipliers, shifters, and adders is to generate a dot product of the 8-bit floating point operands.
20250110812. TECHNOLOGIES TO STORE COMPRESSED DATA_simplified_abstract_(intel corporation)
Inventor(s): Yingqi LU of Portland OR US for intel corporation, Smita KUMAR of Chandler AZ US for intel corporation, Tracy Garrett DRYSDALE of Paradise Valley AZ US for intel corporation, Ranjit MENON of Portland OR US for intel corporation, Toby OPFERMAN of Portland OR US for intel corporation, Deepak GANDIGA SHIVAKUMAR of Beaverton OR US for intel corporation, Stephen DOYLE of Ennis IE for intel corporation, Corey D. GOUGH of Portland OR US for intel corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/544
Abstract: examples described herein relate to a processor to execute the instructions to cause: issue a first call to an application program interface (api) to an accelerator to cause the accelerator to compress data. in some examples, the api is to indicate whether the data is to be preserved in a buffer. in some examples, the api is to indicate a first offset. in some examples, the accelerator is to store the data starting at an address that is the first offset from a beginning address of the buffer allocated in a memory device. in some examples, the accelerator is to store the compressed data starting at a second offset from the beginning address of the buffer while the data is also stored in the buffer.
Inventor(s): Rahul Pal of Bangalore IN for intel corporation, Ashish Gupta of San Jose CA US for intel corporation, William Bainbridge of Palo Alto CA US for intel corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/546
Abstract: techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. in various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (cmb). the target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. communications via the cmb enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. in another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the cmb.
Inventor(s): Ahmad Yasin of Kafr Manda IL for intel corporation, Andreas Kleen of Portland OR US for intel corporation, Jonathan Combs of Austin TX US for intel corporation
IPC Code(s): G06F11/34
CPC Code(s): G06F11/3409
Abstract: techniques for performance monitoring are described. in certain examples, an apparatus (e.g., a processor) includes an execution circuit to execute one or more instructions; a performance monitoring counter; a control register comprising a threshold field; and a performance monitor control circuit to increment the performance monitoring counter in response to a performance monitoring event of the one or more instructions being equal to, but not greater than, the threshold field.
20250110876. DYNAMIC CACHE FILL PRIORIZATION_simplified_abstract_(intel corporation)
Inventor(s): Ashmita Sinha of New Delhi IN for intel corporation, Joseph Nuzman of Haifa IL for intel corporation
IPC Code(s): G06F12/0811
CPC Code(s): G06F12/0811
Abstract: techniques for dynamic cache fill prioritization are described. in an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (mlc) unit including the cache, a local queue to store mlc lookup requests, an external queue to store mlc fill requests, and an mlc access control hardware. the mlc access control hardware is to dynamically switch prioritization of servicing the mlc lookup requests versus servicing the mlc fill requests.
20250110879. PARTITIONED HOME SNOOP FILTER_simplified_abstract_(intel corporation)
Inventor(s): Kiran Kumar Akella of Hyderabad IN for intel corporation, Sai Prashanth Muralidhara of Portland OR US for intel corporation, Devyani Ghosh of Campbell CA US for intel corporation, Robert G. Blankenship of Tacoma WA US for intel corporation
IPC Code(s): G06F12/0831, G06F12/0846
CPC Code(s): G06F12/0831
Abstract: techniques for partitioned home snoop filtering are described. in an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. the home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
20250110903. HARDWARE ACCELERATION OF DICTIONARY COMPRESSION_simplified_abstract_(intel corporation)
Inventor(s): Dongsheng Liang of Shanghai CN for intel corporation, Junyuan Wang of Shanghai CN for intel corporation, Xiaoyan Bo of Shanghai CN for intel corporation, Yuze Xiao of Shanghai CN for intel corporation, Haoxiang Sun of Shanghai CN for intel corporation, Weigang Li of Shanghai CN for intel corporation, Marian Horgan of Mallow IE for intel corporation, Fei Wang of Shannon IE for intel corporation, John J. Browne of Limerick IE for intel corporation, Laurent Coquerel of Raheen IE for intel corporation, Giovanni Cabiddu of Shannon IE for intel corporation, Vijay Sundar Selvamani of Dublin IE for intel corporation, Steven Linsell of Wootton GB for intel corporation, Karthikeyan Gopal of Chennai IN for intel corporation, Deepika Ranganatha of Tuam IE for intel corporation
IPC Code(s): G06F13/28
CPC Code(s): G06F13/28
Abstract: a hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.
20250110909. POOLED MEMORY ADDRESS TRANSLATION_simplified_abstract_(intel corporation)
Inventor(s): Debendra Das Sharma of Saratoga CA US for intel corporation
IPC Code(s): G06F13/40, G06F12/1072, G06F13/16, G06F13/42, G06F15/167
CPC Code(s): G06F13/404
Abstract: a shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. the request includes a node address according to an address map of the computing node. an address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
20250110918. OFFLOADING FUNCTION STREAMS_simplified_abstract_(intel corporation)
Inventor(s): Robert PAWLOWSKI of Beaverton OR US for intel corporation, Vincent CAVE of Hillsboro OR US for intel corporation, Fabio CHECCONI of Fremont CA US for intel corporation, Scott CLINE of Portland OR US for intel corporation, Shruti SHARMA of Beaverton OR US for intel corporation
IPC Code(s): G06F15/78
CPC Code(s): G06F15/7839
Abstract: techniques for offloading function streams are described. in some examples, a function is a sequence of instructions and a stream is a sequence of functions. in some examples, a co-processor is to handle functions and/or function streams provided by a main processor. in some examples, the co-processor includes a plurality of execution resources that at least include one or more of a direct memory access (dma) engine, an atomic engine, and a collectives engine.
Inventor(s): Frederico C. PRATAS of Mirandela ES for intel corporation, Ayose J. FALCON of Barcelona ES for intel corporation, Marc LUPON of Barcelona ES for intel corporation, Fernando LATORRE of Cambridge GB for intel corporation, Pedro LOPEZ of Barcelona ES for intel corporation, Enric HERRERO ABELLANAS of Barcelona ES for intel corporation, Georgios TOURNAVITIS of Barcelona ES for intel corporation
IPC Code(s): G06F17/15, G06F12/0875, G06N3/04, G06N3/063
CPC Code(s): G06F17/153
Abstract: an apparatus and method are described for distributed and cooperative computation in artificial neural networks. for example, one embodiment of an apparatus comprises: an input/output (i/o) interface; a plurality of processing units communicatively coupled to the i/o interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. the processing units may share data including input neurons and weights over the shared input bus.
Inventor(s): John W. Cressman of Hudson MA US for intel corporation, Arun Subbiah of Folsom CA US for intel corporation, Nitya Ananthula of San Jose CA US for intel corporation, Wayne Szeto of Folsom CA US for intel corporation
IPC Code(s): G06F30/31
CPC Code(s): G06F30/31
Abstract: example methods, apparatus, systems and articles of manufacture (e.g., physical computer readable storage media) to quantify effectiveness of clock gating implementations in electronic design automation are disclosed. example methods disclosed herein include executing a first iteration of an electronic design automation (eda) tool with clock gating of an input circuit design enabled to determine a gated power metric for a clock path of the input circuit design, executing a second iteration of the eda tool with clock gating of the input circuit design disabled to determine an ungated power metric for the clock path of the input circuit design, and outputting a first efficiency metric for the clock path of the input circuit design based on the gated power metric and the ungated power metric.
Inventor(s): Rakesh KANDULA of Bangalore IN for intel corporation, Ravishankar D of Mysore IN for intel corporation
IPC Code(s): G06F30/327
CPC Code(s): G06F30/327
Abstract: methods that are useful in semiconductor chip design are presented. a microarchitectural structured flow chart can be processed and converted into register transfer level hardware description language code. processing of the flow chart can include detecting shapes, lines, colors, and text. the shapes that are detected can be rounded, rhombus, and rectangle and a rounded shape can represent a state, a rhombus can represent a decision, and a rectangle can represent an assignment for a finite state machine.
Inventor(s): Han Hua Leong of Butterworth MY for intel corporation, Ting Ting Teh of San Jose CA US for intel corporation
IPC Code(s): G06F30/34
CPC Code(s): G06F30/34
Abstract: integrated circuit devices, methods, and circuitry that program disaggregated dies and programmable logic devices at least partially in parallel are described herein. a host device may program a programmable logic device using a configuration bitstream having a first protocol and sent via a first portion (e.g., first layer) of a communication link. the host device may program disaggregated dies using image files having a second protocol and sent via a second portion (e.g., second layer) of a communication link. the host device may send the configuration data and the image files at a same or overlapping time since the data may be sent in separate layers of the communication link, thereby avoiding interference.
Inventor(s): Anthony Daniel Rhodes of Portland OR US for intel corporation, Celal Savur of Hillsboro OR US for intel corporation, Bhagyashree Desai of Brooklyn NY US for intel corporation, Richard Beckwith of Portland OR US for intel corporation, Giuseppe Raffa of Portland OR US for intel corporation
IPC Code(s): G06N3/0464, G06N3/08
CPC Code(s): G06N3/0464
Abstract: a neural network model for anomaly detection may include convolutional blocks with different spatial scales. the model may be trained with training data, which may be normal data that lacks anomaly. the convolutional blocks may generate embedding features having different spatial scales. a distance between each embedding feature and a corresponding model embedding may be determined. the distances for the embedding features may be accumulated for determining a loss of the model. the model may be trained based on the loss. an accuracy of the trained model may be tested with testing data that has verified anomaly. one or more convolutional blocks may be selected from all the convolutional blocks in the model, e.g., based on the spatial scales of the convolutional blocks and the spatial scale of data on which anomaly detection is to be performed. the selected convolutional block(s) may be used to detect anomaly in the data.
Inventor(s): Gabor LIKTOR of San Francisco CA US for intel corporation, Karthik VAIDYANATHAN of San Francisco CA US for intel corporation, Jefferson AMSTUTZ of Austin TX US for intel corporation, Atsuo KUWAHARA of Portland OR US for intel corporation, Michael DOYLE of Santa Clara CA US for intel corporation, Travis SCHLUESSLER of Berthoud CO US for intel corporation
IPC Code(s): G06T15/00, G06T1/60, G06T15/06
CPC Code(s): G06T15/005
Abstract: apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. for example, one embodiment of an apparatus comprises: single-instruction multiple-data (simd) or single-instruction multiple-thread (simt) execution units (eus) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the eus in a single shader batch upon detection of the triggering event.
Inventor(s): SungYe Kim of Folsom CA US for intel corporation, Collin Allen of San Francisco CA US for intel corporation, Mrutunjayya Mrutunjayya of Hillsboro OR US for intel corporation, Selvakumar Panneer of Portland OR US for intel corporation, Rama Harihara of Santa Clara CA US for intel corporation, Anton Kaplanyan of Mercer Island WA US for intel corporation
IPC Code(s): G06T15/50, G06T1/20, G06T1/60, G06T3/40, G06T15/06
CPC Code(s): G06T15/506
Abstract: described herein is a technique to approximate photorealistic indirect illumination shown in path traced images for dynamic lighting environments using a neural network. given a lightly ray traced image, intermediate buffers from rendering pipeline, and light and camera information, the photorealism of rendered images can be enhanced via the neural network to approximate path traced indirect illumination.
Inventor(s): Mark KOEPER of Beaverton OR US for intel corporation, Andrew MOORE of Cornelius OR US for intel corporation, Sreenivas KOSARAJU of Portland OR US for intel corporation, Nicholas J. KYBERT of Portland OR US for intel corporation, Mengcheng LU of Portland OR US for intel corporation, Atul MADHAVAN of Portland OR US for intel corporation, Sudipto NASKAR of Portland OR US for intel corporation, Wei Z. QIU of Portland OR US for intel corporation, Tiffany R. ZINK of Sheridan OR US for intel corporation
IPC Code(s): H01L21/02, H01L23/48, H01L29/10, H01L29/423
CPC Code(s): H01L21/02178
Abstract: selective dielectric growth directing contact to gate or contact to trench contact are described. in an example, an integrated circuit structure includes a plurality of gate structures above a substrate. a plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. the integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. a dielectric-on-metal (dom) layer is on and is confined to the uppermost surface of the conductive trench contact structures. a gate contact via is on a gate electrode of one of the plurality of gate structures.
Inventor(s): Thomas L. Sounart of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Carlos Bedoya Arroyave of Portland OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation
IPC Code(s): H01L21/67, H01L21/56, H01L21/683, H01L21/762
CPC Code(s): H01L21/67288
Abstract: in one embodiment, a selective transfer process includes forming a layer of integrated circuit (ic) components on a first substrate. the method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the ic components on the first substrate. the method further includes partially bonding the first substrate to the second substrate, where a subset of the ic components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. when the first substrate is separated from the second substrate, the subset of ic components is separated from the first substrate and remain on the second substrate.
Inventor(s): Feras Eid of Chandler AZ US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Brandon M. Rawlings of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Grant M. Kloster of Lake Oswego OR US for intel corporation, Carlos Bedoya Arroyave of Portland OR US for intel corporation
IPC Code(s): H01L21/683, H01L23/00, H01L23/538
CPC Code(s): H01L21/6835
Abstract: an embodiment discloses an electronic device comprising an integrated circuit (ic) die, a stub extending from the ic die; and a mesa structure under the ic die, wherein the ic die and the stub are bonded to the mesa structure.
Inventor(s): Bohan Shan of Chandler AZ US for intel corporation, Ziyin Lin of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Yiqun Bai of Chandler AZ US for intel corporation, Kyle Arrington of Gilbert AZ US for intel corporation, Jose Waimin of Gilbert AZ US for intel corporation, Ryan Carrazzone of Chandler AZ US for intel corporation, Hongxia Feng of Chandler AZ US for intel corporation, Dingying Xu of Chandler AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Minglu Liu of Chandler AZ US for intel corporation, Seyyed Yahya Mousavi of Chandler AZ US for intel corporation, Xinyu Li of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Wei Li of Chandler AZ US for intel corporation, Bin Mu of Tempe AZ US for intel corporation, Mohit Gupta of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Xiaoying Guo of Chandler AZ US for intel corporation, Ashay Dani of Chandler AZ US for intel corporation
IPC Code(s): H01L21/762, H01L21/768, H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L21/76224
Abstract: an apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. other embodiments are also disclosed and claimed.
Inventor(s): Robert May of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Tarek Ibrahim of Mesa AZ US for intel corporation, Lilia May of Chandler AZ US for intel corporation, Jason Gamba of Gilbert AZ US for intel corporation, Benjamin Duong of Phoenix AZ US for intel corporation, Brandon Marin of Gilbert AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation
IPC Code(s): H01L23/29, H01L23/00, H01L23/31, H01L25/00, H01L25/065
CPC Code(s): H01L23/291
Abstract: an ic die package includes first and second ic die on a first surface of a glass layer, a bridge under the first and second ic die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. first interconnects comprising solder couple the bridge with the first and second ic die. second interconnects excluding solder couple the first and second ic die with vias extending through the glass layer to the first package conductive features. third interconnects excluding solder couple the bridge with the second package conductive features. the bridge couples the first and second ic die with each other, and the first and second ic die with the second package conductive features. a pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.
Inventor(s): Tarek Gebrael of Chandler AZ US for intel corporation, Darshan Ravoori of Chandler AZ US for intel corporation, Matthew Magnavita of Chandler AZ US for intel corporation, Aastha Uppal of Chandler AZ US for intel corporation, Xiao Lu of Chandler AZ US for intel corporation
IPC Code(s): H01L23/367, H01L23/498, H01L23/538, H01L25/00, H01L25/10
CPC Code(s): H01L23/367
Abstract: an integrated circuit (ic) device includes a device substrate with front- and backside ic dies and an integrated heat spreader over the backside die. the heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. the backside heat spreader may include a mask layer over a thermally conductive layer. the ic device may include or be coupled to second substrate (such as a motherboard). the backside heat spreader may be thermally coupled to a heat spreader or heat sink by vias through the second substrate. the backside heat spreader may enclose the backside ic die in an electrically conductive cage.
Inventor(s): Carin Ruiz of Portland OR US for intel corporation
IPC Code(s): H01L23/373, C22C26/00, H01L23/367
CPC Code(s): H01L23/3732
Abstract: technologies for diamond composite materials are disclosed. in one embodiment, field-assisted sintering technology (fast) is used to create a diamond composite material that includes diamond particles, copper, and chromium. the chromium can help bond the copper and the diamond particles. the diamond composite material has a high thermal conductivity, such as 500-1,000 w/(m�k). in one embodiment, the diamond composite material may be used in an integrated heat spreader in an integrated circuit component. in other embodiments, the diamond composite material may be used in a heat sink, a cold plate, an internal frame, a chassis, etc.
Inventor(s): Tao CHU of Portland OR US for intel corporation, Minwoo JANG of Portland OR US for intel corporation, Yanbin LUO of Portland OR US for intel corporation, Paul PACKAN of Hillsboro OR US for intel corporation, Conor P. PULS of Portland OR US for intel corporation, Guowei XU of Portland OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Feng ZHANG of Hillsboro OR US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Chia-Ching LIN of Portland OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Chung-Hsun LIN of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation
IPC Code(s): H01L23/48, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: integrated circuit structures having deep via bar width tuning are described. for example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. a plurality of trench contacts is intervening with the plurality of gate lines. a conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.
20250112122. BACKSIDE POWER GATING_simplified_abstract_(intel corporation)
Inventor(s): Kevin P. O'Brien of Portland OR US for intel corporation, Paul Gutwin of Williston VT US for intel corporation, David L. Kencke of Beaverton OR US for intel corporation, Mahmut Sami Kavrik of Eugene OR US for intel corporation, Daniel Chanemougame of Niskayuna NY US for intel corporation, Ashish Verma Penumatcha of Hillsboro OR US for intel corporation, Carl Hugo Naylor of Portland OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Tristan A. Tronic of Aloha OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Rachel A. Steinhardt of Beaverton OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Chi-Yin Cheng of Hillsboro OR US for intel corporation, Yu-Jin Chen of Hillsboro OR US for intel corporation, Tyrone Wilson of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/48, H01L23/528, H01L27/092, H01L29/06, H01L29/18, H01L29/423, H01L29/78
CPC Code(s): H01L23/481
Abstract: integrated circuit (ic) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. in one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation, Aleksandar Aleksov of Chandler AZ US for intel corporation, Leonel Arana of Phoenix AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Benjamin Duong of Phoenix AZ US for intel corporation, Hongxia Feng of Chandler AZ US for intel corporation, Tarek Ibrahim of Mesa AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Tchefor Ndukum of Chandler AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Matthew Tingey of Mesa AZ US for intel corporation
IPC Code(s): H01L23/482, H01L23/00, H01L23/31, H01L23/498, H01L25/065
CPC Code(s): H01L23/4821
Abstract: deep cavity arrangements on integrated circuit packaging an electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (ic) die embedded within the dielectric material and below the upper-most metallization layer. the package also has a metallization pattern within the dielectric material and below the ic die; and a gap within the dielectric material and extending around the metallization pattern.
Inventor(s): Ranjul Balakrishnan of Bangalore IN for intel corporation, Prabhat Ranjan of Bengaluru IN for intel corporation, Prashant Dhirubhai Parmar of Gilbert AZ US for intel corporation, Naren Sreenivas Viswanathan of Gilbert AZ US for intel corporation, Russell Kevin Mortensen of Chandler AZ US for intel corporation
IPC Code(s): H01L23/482, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/4821
Abstract: bridges over metal voids in integrated circuit packages are disclosed. an example a substrate for an electronic circuit comprising a first conductive layer having an aperture extending through the first conductive layer, the aperture aligned with a contact pad, the first conductive layer including an arm extending from a first location on a perimeter of the aperture to a second location on the perimeter of the aperture, and a second conductive layer adjacent to the first conductive layer, the second conductive layer including a metal trace positioned adjacent to the arm, the arm between the metal trace and the contact pad.
Inventor(s): Kimin Jun of Portland OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Veronica Strong of Hillsboro OR US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation
IPC Code(s): H01L23/495, H01L21/48, H01L23/498, H01L23/528
CPC Code(s): H01L23/49513
Abstract: a surface finish on an integrated circuit (ic) die structure or a substrate structure to which an ic die structure is to be bonded has a chemical composition distinct from that of underlying metallization. the surface finish may comprise a cu—ni alloy. optionally, the cu—ni alloy may further comprise mn. alternatively, the surface finish may comprise a noble metal, such as pd, pt, or ru or may comprise self-assembled monolayer (sam) molecules comprising si and c. during the bonding process a biphilic surface on the ic die structure or substrate structure may facilitate liquid droplet-based fine alignment of the ic die structure to a host structure. prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.
Inventor(s): Bohan SHAN of Chandler AZ US for intel corporation, Jesse JONES of Chandler AZ US for intel corporation, Zhixin XIE of Chandler AZ US for intel corporation, Bai NIE of Chandler AZ US for intel corporation, Shaojiang CHEN of Chandler AZ US for intel corporation, Joshua STACEY of Chandler AZ US for intel corporation, Mitchell PAGE of Mesa AZ US for intel corporation, Brandon C. MARIN of Gilbert AZ US for intel corporation, Jeremy D. ECTON of Gilbert AZ US for intel corporation, Nicholas S. HAEHN of Scottsdale AZ US for intel corporation, Astitva TRIPATHI of Mesa AZ US for intel corporation, Yuqin LI of Chandler AZ US for intel corporation, Edvin CETEGEN of Chandler AZ US for intel corporation, Jason M. GAMBA of Gilbert AZ US for intel corporation, Jacob VEHONSKY of Chandler AZ US for intel corporation, Jianyong MO of Chandler AZ US for intel corporation, Makoyi WATSON of Phoenix AZ US for intel corporation, Shripad GOKHALE of Gilbert AZ US for intel corporation, Mine KAYA of Scottsdale AZ US for intel corporation, Kartik SRINIVASAN of Gilbert AZ US for intel corporation, Haobo CHEN of Chandler AZ US for intel corporation, Ziyin LIN of Chandler AZ US for intel corporation, Kyle ARRINGTON of Gilbert AZ US for intel corporation, Jose WAIMIN of Gilbert AZ US for intel corporation, Ryan CARRAZZONE of Chandler AZ US for intel corporation, Hongxia FENG of Chandler AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Dingying David XU of Chandler AZ US for intel corporation, Hiroki TANAKA of Gilbert AZ US for intel corporation, Ashay DANI of Chandler AZ US for intel corporation, Praveen SREERAMAGIRI of Gilbert AZ US for intel corporation, Yi LI of Chandler AZ US for intel corporation, Ibrahim EL KHATIB of Chandler AZ US for intel corporation, Aaron GARELICK of Chandler AZ US for intel corporation, Robin MCREE of Chandler AZ US for intel corporation, Hassan AJAMI of Chandler AZ US for intel corporation, Yekan WANG of Chandler AZ US for intel corporation, Andrew JIMENEZ of Mesa AZ US for intel corporation, Jung Kyu HAN of Chandler AZ US for intel corporation, Hanyu SONG of Chandler AZ US for intel corporation, Yonggang Yong LI of Chandler AZ US for intel corporation, Mahdi MOHAMMADIGHALENI of Phoenix AZ US for intel corporation, Whitney BRYKS of Tempe AZ US for intel corporation, Shuqi LAI of Phoenix AZ US for intel corporation, Jieying KONG of Chandler AZ US for intel corporation, Thomas HEATON of Gilbert AZ US for intel corporation, Dilan SENEVIRATNE of Phoenix AZ US for intel corporation, Yiqun BAI of Chandler AZ US for intel corporation, Bin MU of Tempe AZ US for intel corporation, Mohit GUPTA of Chandler AZ US for intel corporation, Xiaoying GUO of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/15
CPC Code(s): H01L23/49822
Abstract: embodiments disclosed herein include apparatuses with glass core package substrates. in an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. a sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. in an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. in an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
Inventor(s): Srinivas Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Sameer Paital of Mesa AZ US for intel corporation, Zhixin Xie of Chandler AZ US for intel corporation, Rahul Manepalli of Chandler AZ US for intel corporation, Jieying Kong of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/15
CPC Code(s): H01L23/49827
Abstract: microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (tgvs) extending through the layer of glass. individual tgvs comprise a tgv sidewall, an organic dielectric layer on the tgv sidewall and a conductive layer on the organic dielectric layer.
Inventor(s): Abdallah BACHA of Munich DE for intel corporation, Thomas WAGNER of Regelsbach DE for intel corporation, Cindy MUIR of Tempe OR for intel corporation, Mohan Prashanth JAVARE GOWDA of Ottobrunn DE for intel corporation, Stephan STOECKL of Schwandorf DE for intel corporation, Wolfgang MOLZER of Ottobrunn DE for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/31, H01L23/48, H01L23/538, H01L25/065
CPC Code(s): H01L23/49827
Abstract: embodiments herein relate to systems, apparatuses, or processes for forming a die that has active circuitry within the die and also one or more vias that extend through the die that are electrically isolated from the active circuitry. in embodiments, the active circuitry may be within a region within a die, for example in the center of the die, and the vias may be in an extended area around the active circuitry of the die. in embodiments, an existing die may be provided, and an extended area may be formed on the existing die into which the vias may be placed. other embodiments may be described and/or claimed.
Inventor(s): Rahul BHURE of Mesa AZ US for intel corporation, Mitchell PAGE of Mesa AZ US for intel corporation, Joseph PEOPLES of Gilbert AZ US for intel corporation, Jieying KONG of Chandler AZ US for intel corporation, Nicholas S. HAEHN of Scottsdale AZ US for intel corporation, Astitva TRIPATHI of Mesa AZ US for intel corporation, Bainye Francoise ANGOUA of Phoenix AZ US for intel corporation, Yosef KORNBLUTH of Phoenix AZ US for intel corporation, Daniel ROSALES-YEOMANS of Gilbert AZ US for intel corporation, Joshua STACEY of Chandler AZ US for intel corporation, Aaditya Anand CANDADAI of Chandler AZ US for intel corporation, Yonggang Yong LI of Chandler AZ US for intel corporation, Tchefor NDUKUM of Chandler AZ US for intel corporation, Scott COATNEY of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Jesse JONES of Chandler AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Dilan SENEVIRATNE of Phoenix AZ US for intel corporation, Matthew ANDERSON of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/15
CPC Code(s): H01L23/49838
Abstract: embodiments disclosed herein include package substrates with a glass core. in an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. in an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. in an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. in an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.
Inventor(s): Mohamed R. Saber of College Station TX US for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H05K1/02, H05K1/03, H05K1/11
CPC Code(s): H01L23/49894
Abstract: disclosed herein are microelectronic assemblies and related devices and methods. in some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (tgvs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy monomers, and the thermal isomeric linkages including a cis-dibenzocyclooctane (dbco) moiety or a tetra derivative dbco moiety. in some embodiments, the dielectric material includes an epoxy having thermal isomeric epoxy monomers including a cis-dbco moiety or a tetra derivative dbco moiety, non-thermal isomeric epoxy monomers, and non-thermal isomeric linkages. in some embodiments, the dielectric material includes a bismaleimide resin or a polyimide resin having non-thermal isomeric monomers and thermal isomeric monomers including a cis-dbco moiety or a tetra derivative dbco moiety.
Inventor(s): Aleksandar Aleksov of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: methods and apparatus are disclosed to improve interconnect structures in integrated circuit packages. an example integrated circuit (ic) package includes a first interconnect structure positioned on a first surface of an underlying substrate; a second interconnect structure positioned on the first surface of the underlying substrate, the second interconnect structure adjacent to the first interconnect structure; and a first dielectric material between the first and second interconnect structures, the first dielectric material including an enclosed trench within a space between the first and second interconnect structures.
Inventor(s): Xi Li of Chandler AZ US for intel corporation, Chuanzhao Yu of Phoenix AZ US for intel corporation, Yazan Hejazin of Chandler AZ US for intel corporation, Marco Bresciani of Scottsdale AZ US for intel corporation, Hyun Yoon of Gilbert AZ US for intel corporation, Lichung Chang of Mesa AZ US for intel corporation
IPC Code(s): H01L23/522, H01L23/48, H01L27/06
CPC Code(s): H01L23/5227
Abstract: an integrated circuit device with front- and back-side metals may include coils in interconnect structures on one or both sides of a semiconductor substrate. the coil(s) may include vias extending through (and coupling wires on both sides of) the substrate. the coil(s) may include multiple turns or loops. the coil(s) may be on one side, and parallel to, the substrate. coils may be orthogonal or parallel to each other. a resistor may have smaller resistor segments on both sides of the substrate coupled by through-substrate vias. a capacitor may utilize through-substrate vias as plates. through-substrate vias may inhibit eddy currents in the substrate. a cage of wires and through-substrate vias may shield devices within the cage from interfering fields external to the cage.
Inventor(s): Hwichan JUN of Portland OR US for intel corporation, Lee ROCKFORD of Portland OR US for intel corporation
IPC Code(s): H01L23/528, H01L23/544, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L23/528
Abstract: structures having registration marks for dual-sided devices are described. in an example, an integrated circuit structure includes a front side structure. the front side structure includes a device layer comprising a plurality of nanowire-based or fin-based transistors and a pad laterally adjacent to the plurality of nanowire-based or fin-based transistors, the pad having first grating structures aligned along an x-direction and second grating structures aligned along a y-direction therein, the first and second grating structures exposed at a backside surface of the front side structure. the front-side also includes a plurality of metallization layers above the plurality of nanowire-based or fin-based transistors. the integrated circuit structure also includes a backside structure below the plurality of nanowire-based or fin-based transistors of the device layer of the front side structure, the backside structure comprising backside metal layers and vias.
Inventor(s): Inanc Meric of Portland OR US for intel corporation, Keun Woo Park of Hillsboro OR US for intel corporation, Jeffrey Hicks of Banks OR US for intel corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/48, H01L23/522, H01L27/092
CPC Code(s): H01L23/5286
Abstract: integrated circuit (ic) devices and systems with virtual ground nets, and methods of forming the same, are disclosed herein. in one embodiment, an integrated circuit die includes a device layer with transistors, a first interconnect over the device layer, and a second interconnect under the device layer. moreover, the first interconnect includes ground traces, which are electrically coupled to each other in the first interconnect or the second interconnect.
Inventor(s): Kimin Jun of Portland OR US for intel corporation, Scott Clendenning of for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Robert Jordan of Portland OR US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation, Jiun-Ruey Chen of Hillsboro OR US for intel corporation, Tayseer Mahdi of Hillsboro OR US for intel corporation, Carlos Felipe Bedoya Arroyave of Portland OR US for intel corporation, Shashi Bhushan Sinha of Hillsboro OR US for intel corporation, Anandi Roy of Hillsboro OR US for intel corporation, Tristan Tronic of Aloha OR US for intel corporation, Dominique Adams of Portland OR US for intel corporation, William Brezinski of Beaverton OR US for intel corporation, Richard Vreeland of Beaverton OR US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Brian Barley of Beaverton OR US for intel corporation, Jeffery Bielefeld of Forest Grove OR US for intel corporation
IPC Code(s): H01L23/532, H01L21/48, H01L23/498, H01L23/528
CPC Code(s): H01L23/53214
Abstract: hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. one or both of an integrated circuit (ic) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. the protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. the hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the ic die to self-align. a hybrid bond is formed by evaporating the droplet and a subsequent anneal. the hydrophobic structures contain the liquid droplet for alignment during bonding.
20250112156. BARRIER LAYERS FOR INTERCONNECTS_simplified_abstract_(intel corporation)
Inventor(s): Gowtham Sriram JAWAHARRAM of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/532, H01L21/768, H01L23/522
CPC Code(s): H01L23/53238
Abstract: barrier layers comprised of alloys of vanadium in tantalum are provided. the barrier layers are useful for conducting interconnects, such as copper interconnects, for semiconductor devices. interconnects can be in dielectric layers which can be back-end metallization layers.
Inventor(s): Andrew P. COLLINS of Chandler AZ US for intel corporation, Jian Yong XIE of Chandler AZ US for intel corporation, Aruna KUMAR of Bangalore IN for intel corporation, Rinkle JAIN of Sherwood OR US for intel corporation, Basavaraj KANTHI of Bangalore IN for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L25/065, H10B80/00
CPC Code(s): H01L23/5381
Abstract: embodiments disclosed herein include an apparatus for bump translation. in an embodiment, the apparatus includes a substrate with a first bump field with a first height and a first depth on the substrate, where the first depth is orthogonal to the first height, and where the first bump field further comprises a first pitch in a direction of the first height. in an embodiment, the apparatus includes a second bump field with a second height and a second depth on the substrate, where the second depth is orthogonal to the second height, and where the second bump field comprises a second pitch in a direction of the second height, where the second pitch is smaller than the first pitch. embodiments include a third bump field with a third height and the second depth, where a sum of the second height and the third height is equal to the first height.
Inventor(s): Minglu Liu of Chandler AZ US for intel corporation, Seyyed Yahya Mousavi of Chandler AZ US for intel corporation, Yingying Zhang of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Andrey Gunawan of Paradise Valley AZ US for intel corporation, Yosuke Kanaoka of Chandler AZ US for intel corporation, Yiqun Bai of Chandler AZ US for intel corporation, Ziyin Lin of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Dingying Xu of Chandler AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Hong Seung Yeon of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/31
CPC Code(s): H01L23/5381
Abstract: methods and apparatus to connect interconnect bridges to package substrates are disclosed. an example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.
Inventor(s): Zheng Kang of Chandler AZ US for intel corporation, Tchefor Ndukum of Chandler AZ US for intel corporation, Yosuke Kanaoka of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jefferson Kaplan of Chandler AZ US for intel corporation, Yonggang Yong Li of Chandler AZ US for intel corporation, Minglu Liu of Chandler AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Shriya Seshadri of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Deniz Turan of Chandler AZ US for intel corporation, Vishal Bhimrao Zade of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00
CPC Code(s): H01L23/5383
Abstract: an electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (ic) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the ic die. a downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. the lower dielectric material layer has an upper facing surface facing in a direction of the ic die adjacent the conductive feature that is vertically offset from the horizontal plane.
Inventor(s): Pratyush Mishra of Tempe AZ US for intel corporation, Pratyasha Mohapatra of Hillsboro OR US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Mahdi Mohammadighaleni of Phoenix AZ US for intel corporation, Joshua Stacey of Chandler AZ US for intel corporation, Travis Palmer of San Diego CA US for intel corporation, Yosef Kornbluth of Phoenix AZ US for intel corporation, Kuang Liu of Quen Creek AZ US for intel corporation, Astitva Tripathi of Mesa AZ US for intel corporation, Yuqin Li of Chandler AZ US for intel corporation, Rengarajan Shanmugam of Tempe AZ US for intel corporation, Xing Sun of Chandler AZ US for intel corporation, Brian Balch of Chandler AZ US for intel corporation, Darko Grujicic of Chandler AZ US for intel corporation, Jieying Kong of Chandler AZ US for intel corporation, Nicholas Haehn of Scottsdale AZ US for intel corporation, Jacob Vehonsky of Chandler AZ US for intel corporation, Mitchell Page of Mesa AZ US for intel corporation, Vincent Obiozo Eze of Chandler AZ US for intel corporation, Daniel Wandera of Chandler AZ US for intel corporation, Sameer Paital of Mesa AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/15, H01L25/065
CPC Code(s): H01L23/5384
Abstract: an ic die package includes a substrate comprising glass and a plurality of holes extending through the glass. a via metallization is present within the holes. a liner is between the via metallization and the glass. the liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an mxene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. a polymer layer may be formed by electrodeposition of charged nanoparticles.
20250112164. CONTROLLING SUBSTRATE BUMP HEIGHT_simplified_abstract_(intel corporation)
Inventor(s): Bohan SHAN of Chandler AZ US for intel corporation, Onur OZKAN of Scottsdale AZ US for intel corporation, Ryan CARRAZZONE of Chandler AZ US for intel corporation, Rui ZHANG of Chandler AZ US for intel corporation, Haobo CHEN of Chandler AZ US for intel corporation, Ziyin LIN of Chandler AZ US for intel corporation, Yiqun BAI of Chandler AZ US for intel corporation, Kyle ARRINGTON of Gilbert AZ US for intel corporation, Jose WAIMIN of Gilbert AZ US for intel corporation, Hongxia FENG of Chandler AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Dingying David XU of Chandler AZ US for intel corporation, Bin MU of Tempe AZ US for intel corporation, Mohit GUPTA of Chandler AZ US for intel corporation, Jeremy D. ECTON of Gilbert AZ US for intel corporation, Brandon C. MARIN of Gilbert AZ US for intel corporation, Xiaoying GUO of Chandler AZ US for intel corporation, Steve S. CHO of Chandler AZ US for intel corporation, Ali LEHAF of Phoenix AZ US for intel corporation, Venkata Rajesh SARANAM of Phoenix AZ US for intel corporation, Shripad GOKHALE of Gilbert AZ US for intel corporation, Kartik SRINIVASAN of Gilbert AZ US for intel corporation, Edvin CETEGEN of Chandler AZ US for intel corporation, Mine KAYA of Scottsdale AZ US for intel corporation, Nicholas S. HAEHN of Scottsdale AZ US for intel corporation, Deniz TURAN of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L25/065
CPC Code(s): H01L23/5385
Abstract: a device comprises a substrate comprising a plurality of build-up layers and a cavity. a bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. a plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.
Inventor(s): Brandon Marin of Gilbert AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Robert May of Chandler AZ US for intel corporation, Srinivas Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation, Numair Ahmed of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Benjamin Taylor Duong of Phoenix AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Xiao Liu of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Shruti Sharma of Chandler AZ US for intel corporation, Mollie Stewart of Lake Oswego OR US for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00
CPC Code(s): H01L23/5385
Abstract: anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. an example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.
Inventor(s): Kimberly Pierce of Beaverton OR US for intel corporation, Marni Nabors of Portland OR US for intel corporation, Nidhi Khandelwal of Portland OR US for intel corporation, Keith Zawadzki of Portland OR US for intel corporation
IPC Code(s): H01L23/544, G03F7/09, H01L21/768, H01L23/528, H01L23/58
CPC Code(s): H01L23/544
Abstract: an integrated circuit (ic) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. a functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. the ic device may include multiple such functional blocks spanning lithographic fields. the lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. the multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. the lithographic seam may interface with wafer finishing collaterals (such as guard rings).
20250112168. HYBRID BONDING WITH EMBEDDED ALIGNMENT MARKERS_simplified_abstract_(intel corporation)
Inventor(s): Omkar G. Karhade of Chandler AZ US for intel corporation, Nitin A. Deshpande of Chandler AZ US for intel corporation, Gwang-Soo Kim of Portland OR US for intel corporation, Harini Kilambi of Portland OR US for intel corporation, Han Ju Lee of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/544, H01L23/00, H01L23/522, H01L23/538, H01L25/065
CPC Code(s): H01L23/544
Abstract: alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. the alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. a reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. the alignment markers can further be used to align a wafer bonding layer to the reconstituted wafer. the wafer bonding layer can be used in attaching the reconstituted wafer to an interposer, another wafer, or another microelectronic structure. the alignment markers are located outside an outer lateral boundary of the integrated circuit dies (such as between integrated circuit dies) and are not connected to any metal lines in the integrated circuit dies in the reconstituted wafer.
Inventor(s): Kimin Jun of Portland OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/31
CPC Code(s): H01L23/562
Abstract: a surface of an integrated circuit (ic) die structure and a substrate to which the ic die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the ic die structure to the substrate. to ensure warpage of the ic die structure does not interfere with droplet-based fine alignment process, an ic die structure of greater thickness is aligned to the substrate and thickness of the ic die structure subsequently reduced. in some embodiments, a back side of the ic die structure is polished back post attachment. in some alternative embodiments, the ic die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
20250112174. ANNEALED SHAPE MEMORY ALLOY ON A SUBSTRATE_simplified_abstract_(intel corporation)
Inventor(s): Siddarth KUMAR of Chandler AZ US for intel corporation, Shripad GOKHALE of Gilbert AZ US for intel corporation, Edvin CETEGEN of Chandler AZ US for intel corporation, Praneeth NAMPALLY of Chandler AZ US for intel corporation, Astitva TRIPATHI of Mesa AZ US for intel corporation, Sairam AGRAHARAM of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L21/3205
CPC Code(s): H01L23/562
Abstract: embodiments herein relate to systems, apparatuses, techniques or processes for forming an annealed shape metal alloy (sma) on a wafer or a die complex. in embodiments, the annealed sma, when heated above a transition temperature, may enter an austenite phase and return to the shape that the wafer or die complex had when it was annealed. in embodiments, this may maintain a shape of a wafer or a die complex during higher temperature processing, for example during reflow, when the package undergoes fabrication. other embodiments may be described and/or claimed.
Inventor(s): Brandon C. Marin of Gilbert AZ US for intel corporation, Jesse C. Jones of Chandler AZ US for intel corporation, Yosef Kornbluth of Phoenix AZ US for intel corporation, Mitchell Page of Mesa AZ US for intel corporation, Soham Agarwal of Chandler AZ US for intel corporation, Fanyi Zhu of Gilbert AZ US for intel corporation, Shuren Qu of Gilbert AZ US for intel corporation, Hanyu Song of Chandler AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Yonggang Li of Chandler AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Nicholas Haehn of Scottsdale AZ US for intel corporation, Astitva Tripathi of Mesa AZ US for intel corporation, Mohamed R. Saber of College Station TX US for intel corporation, Sheng Li of Gilbert AZ US for intel corporation, Pratyush Mishra of Tempe AZ US for intel corporation, Benjamin T. Duong of Phoenix AZ US for intel corporation, Kari Hernandez of Phoenix AZ US for intel corporation, Praveen Sreeramagiri of Gilbert AZ US for intel corporation, Yi Li of Chandler AZ US for intel corporation, Ibrahim El Khatib of Chandler AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Mahdi Mohammadighaleni of Phoenix AZ US for intel corporation, Joshua Stacey of Chandler AZ US for intel corporation, Travis Palmer of San Diego CA US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Robin Shea McRee of Chandler AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/13, H01L23/15, H01L25/065
CPC Code(s): H01L23/562
Abstract: various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. in one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. in another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. in yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
Inventor(s): Feras Eid of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Michael Baker of Gilbert AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Xavier Brun of Hillsboro OR US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L21/768, H01L21/8234, H01L23/528, H01L29/786
CPC Code(s): H01L23/564
Abstract: hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. an integrated circuit (ic) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. a liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. a hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. ic structures including the ic die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.
Inventor(s): Brandon Christian Marin of Gilbert AZ US for intel corporation, Tarek A. Ibrahim of Mesa AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ US for intel corporation
IPC Code(s): H01L23/64, H01F17/00, H01F17/06, H01L23/15, H01L23/498
CPC Code(s): H01L23/645
Abstract: techniques for a coaxial inductor in a glass core are disclosed. in an illustrative embodiment, an inductor is positioned in a cavity of a glass core. the inductor includes a conductive via extending through the glass core surrounded by a magnetic material. a buffer layer is positioned between the edges of the cavity of the glass core and the inductor. the buffer can prevent or mitigate any stress caused by changes in temperature and different coefficients of thermal expansion of the glass core and the inductor. the inductor may form part of a fully integrated voltage regulator (fivr), which provides a stable voltage source to a semiconductor die such as a processor.
Inventor(s): Feras Eid of Chandler OR US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation, Xavier Brun of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/00, H01L23/367, H01L25/065
CPC Code(s): H01L24/05
Abstract: hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. an integrated circuit (ic) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. the hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. after the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. ic structures including the ic die and portions of the substrate are segmented and assembled.
Inventor(s): Thomas Sounart of Chandler AZ US for intel corporation, Michael Baker of Gilbert AZ US for intel corporation, Seyed Hadi Zandavi of Pheonix AZ US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. one or both of an integrated circuit (ic) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. the hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the ic die to self-align. the liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. a hybrid bond is formed by evaporating the droplet and a subsequent anneal.
Inventor(s): Feras Eid of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: a surface of at least one of an integrated circuit (ic) die structure or a substrate structure to which the ic die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the ic die structure to the substrate structure. a biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. the inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the ic die structure and a bonding surface of the substrate structure during placement. the inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting ic die edges may also be non-orthogonal.
Inventor(s): Kimin Jun of Portland OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, YI Shi of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/538
CPC Code(s): H01L24/08
Abstract: a surface of an integrated circuit (ic) die structure or a host structure to which the ic die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the ic die structure to the substrate. hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another ic die structure or substrate structure.
Inventor(s): Georgios C. Dogiamis of Chandler AZ US for intel corporation, Qiang Yu of Saratoga CA US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L21/683, H01L23/538, H01L25/00, H01L25/18
CPC Code(s): H01L24/08
Abstract: methods of selectively transferring integrated circuit (ic) components between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a release layer and a layer of ic components over the release layer is received, and a second substrate with one or more adhesive areas is received. the layer of ic components may include one or more antennas, interconnects, inductors, capacitors, or transformers. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
Inventor(s): Xiao Lu of Chandler AZ US for intel corporation, Sangeon Lee of Chandler AZ US for intel corporation, Jiaqi Wu of Chandler AZ US for intel corporation, Tingting Gao of Chandler AZ US for intel corporation, Matthew T. Magnavita of Chandler AZ US for intel corporation, Ravindranath V. Mahajan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/14
Abstract: in one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. the substrate includes first reservoirs comprising gallium-based liquid metal (lm), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. the component includes circuitry and conductive contacts connected to the circuitry. each contact defines a cavity and a portion of each conductive contact is within a respective first reservoir of the substrate such that it is in contact with the lm in the first reservoir. the component further includes dielectric lines between the conductive contacts, and each dielectric line is at least partially within a respective first channel of the substrate.
Inventor(s): Thomas WAGNER of Regelsbach DE for intel corporation, Pouya TALEBBEYDOKHTI of Mesa AZ US for intel corporation, Stephan STOECKL of Schwandorf DE for intel corporation, Lizabeth KESER of San Diego CA US for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L23/13, H01L23/48, H01L23/498, H01L25/00, H01L25/065, H01L25/10
CPC Code(s): H01L24/16
Abstract: a semiconductor package comprises an interposer with at least one open area through the interposer. a first die is connected to a first side of the interposer. a second die is connected to a second side of the interposer. at least one metal pillar is connected to the first die that extends through the open area of the interposer and connects to the second die to provide a direct die-to-die connection through the interposer.
20250112196. SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES_simplified_abstract_(intel corporation)
Inventor(s): Feras Eid of Chandler AZ US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Brandon M. Rawlings of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Shawna M. Liff of Scottsdale AZ US for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L21/683, H01L23/373, H01L23/38, H01L23/433, H01L23/538, H10N19/00
CPC Code(s): H01L24/32
Abstract: an embodiment discloses an electronic device, comprising an integrated circuit (ic) die, a mesa structure formed on the ic die, and a die bonded to the ic die through the mesa structure.
Inventor(s): Pratyasha Mohapatra of Hillsboro OR US for intel corporation, Kyle Davidson of Hillsboro OR US for intel corporation, Brian Franco of Portland OR US for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/73
Abstract: an apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. other embodiments are also disclosed and claimed.
Inventor(s): Thomas Sounart of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Michael Baker of Gilbert AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Wenhao Li of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/80
Abstract: hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. first-level integrated circuit (ic) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. the hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the ic die to self-align. a hybrid bond is formed by evaporating the droplet followed by anneal. hybrid bonding regions of second-level ic dies are similarly bonded to hybrid bonding regions on backsides of the first-level ic dies. this is repeated for any number of subsequent levels of ic dies. ic structures including the bonded ic dies and portions of the base substrate are segmented and assembled.
Inventor(s): Adel Elsherbini of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Thomas Sounart of Chandler AZ US for intel corporation, Yi Shi of Chandler AZ US for intel corporation, Shawna Liff of Scottsdale AZ US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Michael Baker of Gilbert AZ US for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR US for intel corporation, Chien-An Chen of San Jose CA US for intel corporation
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/498, H01L25/065
CPC Code(s): H01L24/80
Abstract: a surface of an integrated circuit (ic) die structure and a substrate to which the ic die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the ic die structure to the substrate. to ensure warpage of the ic die structure does not interfere with droplet-based fine alignment process, an ic die structure of greater thickness is aligned to the substrate and thickness of the ic die structure subsequently reduced. in some embodiments, a back side of the ic die structure is polished back post attachment. in some alternative embodiments, the ic die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
Inventor(s): Abdallah BACHA of Munich DE for intel corporation, Cindy MUIR of Tempe AZ US for intel corporation, Mohan Prashanth JAVARE GOWDA of Ottobrunn DE for intel corporation, Stephan STOECKL of Schwandorf DE for intel corporation, Thomas WAGNER of Regelsbach DE for intel corporation, Wolfgang MOLZER of Ottobrunn DE for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/367, H01L23/538, H01L25/10, H10B80/00
CPC Code(s): H01L25/0652
Abstract: embodiments herein relate to systems, apparatuses, or processes for packages that include substrates that include one or more die in a cavity within the substrate, where sides and a bottom of the cavity are lined with a heat spreader, or tim, material that is thermally coupled to a side of the substrate using thermally conductive vias. in embodiments, thermally conductive vias may be thermally coupled with the heat spreader at the side of the substrate. other embodiments may be described and/or claimed.
Inventor(s): Adel Elsherbini of Chandler AZ US for intel corporation, Julien Sebot of Portland OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Shawna M. Liff of Scottsdale AZ US for intel corporation, Carleton L. Molnar of Northborough MA US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation
IPC Code(s): H01L25/065, G06F12/0811, G06F12/0897, H01L23/00, H01L23/498, H01L23/538, H10B80/00
CPC Code(s): H01L25/0652
Abstract: an embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an l1 cache, an l2 cache, or both an l1 cache and an l2 cache, and wherein the first die or the second die is bonded to an adhesive area.
Inventor(s): Prashant Majhi of San Jose CA US for intel corporation, Nitin A. Deshpande of Chandler AZ US for intel corporation, Omkar G. Karhade of Chandler AZ US for intel corporation, Surhud V. Khare of Buffalo NY US for intel corporation
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/538, H01L25/00
CPC Code(s): H01L25/0652
Abstract: input/output (i/o) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. die-to-die i/o routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. embedded bridges or chiplets or not used for die-to-die i/o routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.
Inventor(s): Eduardo DE MESA of Munich DE for intel corporation, Abdallah BACHA of Munich DE for intel corporation, Jan PROSCHWITZ of Riesa DE for intel corporation, Georg SEIDEMANN of Landshut DE for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/053, H01L23/538, H01L25/00, H10B80/00
CPC Code(s): H01L25/0655
Abstract: embodiments herein relate to systems, apparatuses, techniques or processes for forming a package that includes a mold compound on a first surface of a redistribution layer, where the mold compound includes one or more cavities, and wherein one or more dies are placed within the cavities. in embodiments, one or more dies may be placed on the second surface of the redistribution layer. in embodiments, the dies, mold compound, and redistribution layer may have different coefficients of thermal expansion, in order to reduce warpage of the package during manufacture and operation. other embodiments may be described and/or claimed.
20250112208. SELECTIVE LAYER TRANSFER WITH GLASS PANELS_simplified_abstract_(intel corporation)
Inventor(s): Adel Elsherbini of Chandler AZ US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Shawna M. Liff of Scottsdale AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/15
CPC Code(s): H01L25/0655
Abstract: methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (ic) component on each respective mesa structure. the mesa structures have similar footprints as the ic components, and may be formed on or integrated with the glass layer.
Inventor(s): Andrew COLLINS of Chandler AZ US for intel corporation, Jianyong XIE of Chandler AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/528
CPC Code(s): H01L25/0655
Abstract: apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. in embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. the semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. other embodiments may be described and/or claimed.
20250112210. FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Han Wui Then of Portland OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Georgios C. Dogiamis of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation
IPC Code(s): H01L25/065, H01L21/683, H01L21/8238, H01L23/00
CPC Code(s): H01L25/0657
Abstract: methods of selectively transferring integrated circuit (ic) components between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a release layer and a layer of ic components over the release layer is received, and a second substrate with one or more adhesive areas is received. the layer of ic components may include one or more transistors that contain one or more group iii-v materials. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
Inventor(s): Qiang Yu of Saratoga CA US for intel corporation, Georgios C. Dogiamis of Chandler AZ US for intel corporation, Said Rami of Portland OR US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation
IPC Code(s): H01L25/18, H01L21/48, H01L21/683, H01L23/00, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: methods of selectively transferring integrated circuit (ic) components between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a release layer and a layer of ic components over the release layer is received, and a second substrate with one or more adhesive areas is received. the layer of ic components may include one or more thick gate oxide transistors, group iii-v transistors, varactors, or electrostatic discharge protection devices. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
20250112218. SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS_simplified_abstract_(intel corporation)
Inventor(s): Brandon M. Rawlings of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Richard F. Vreeland of Beaverton OR US for intel corporation
IPC Code(s): H01L25/00, H01L21/683, H01L25/075
CPC Code(s): H01L25/50
Abstract: in one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (ic) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of ic components on the first substrate to respective bonding structures on the second substrate. the process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. the process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of ic components on the first substrate to respective bonding structures on the third substrate.
20250112357. SEMICONDUCTOR PACKAGE WITH RFIC AND ANTENNA_simplified_abstract_(intel corporation)
Inventor(s): Zhen ZHOU of Chandler AZ US for intel corporation, Tae Young YANG of Portland OR US for intel corporation, Shuhei YAMADA of Vancouver WA US for intel corporation, Tolga ACIKALIN of San Jose CA US for intel corporation, Renzhi LIU of Portland OR US for intel corporation, Kenneth FOUST of Beaverton OR US for intel corporation, Bryce HORINE of Portland OR US for intel corporation
IPC Code(s): H01Q1/22, H01L23/31, H01L23/538, H01L25/00, H01L25/065, H01Q1/48, H01Q5/40, H01Q9/04
CPC Code(s): H01Q1/2283
Abstract: the present disclosure relates to a semiconductor package comprising a substrate, a radio frequency integrated circuit attached to the substrate, optionally at least one semiconductor die attached to the substrate and coupled to a radio frequency integrated circuit (rfic) via one or more signal lines, a molding compound encapsulating the rfic and the optional semiconductor die, and an antenna formed on the molding compound and coupled to the rfic.
20250112365. OMNI-DIRECTIONAL, MINIATURIZED ANTENNA SYSTEM_simplified_abstract_(intel corporation)
Inventor(s): Walid EL HAJJ of Antibes FR for intel corporation, Serge DAO of Vallauris FR for intel corporation, Jayprakash THAKUR of Bangalore IN for intel corporation, Nawfal ASRIH of Mandelieu-la-Napoule FR for intel corporation, Wilfrid LEFEVRE of Valbonne FR for intel corporation, Yoni KAHANA of Kfar Hess IL for intel corporation
IPC Code(s): H01Q5/385, H01Q1/38, H01Q1/50, H01Q21/28
CPC Code(s): H01Q5/385
Abstract: disclosed herein are devices, systems, and methods for an antenna system that may be used not only for wireless communications but also for other antenna-based applications such as proximity sensing, ranging, and angle of arrival measurements. the antenna system includes a plurality of antenna groups that include a first antenna group and a second antenna group. the first antenna group includes a parasitic element and a radiating element fed by a antenna port. the second antenna group includes a second parasitic element and a second radiating element fed by a second antenna port. the antenna system also includes a ground plane coupled to the first antenna group and the second antenna group. the first antenna group may be separated from and mirrored by the second antenna group.
Inventor(s): Richard Canham of West Richland WA for intel corporation, Ernesto Borboa Lizarraga of Zapopan MX for intel corporation, Daniel Neumann of Tualatin OR US for intel corporation, Shelby Ferguson of El Dorado Hills CA US for intel corporation, Eric Buddrius of Hillsboro OR US for intel corporation, Hardikkumar Prajapati of Chandler AZ US for intel corporation, Kirk Wheeler of Chandler AZ US for intel corporation, Steven Klein of Chandler AZ US for intel corporation, Shaun Immeker of Wilton CA US for intel corporation, Jeffory L. Smalley of East Olympia WA US for intel corporation
IPC Code(s): H01R12/85
CPC Code(s): H01R12/85
Abstract: a semiconductor package carrier used to support a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) as the semiconductor package is moved from a shipping tray to a land grid array (lga) socket during assembly of an electronic device. the semiconductor package carrier including a carrier body including a plurality of support structures arranged to support a portion of the semiconductor package. the semiconductor package carrier further including a locking structure moveable between a first position and a second position, wherein the first position allows the support structures to receive the semiconductor package and the second position secures the semiconductor package to the carrier body. in some embodiments, the semiconductor package carrier may also include a thermal interface material (tim) breaker to facilitate removal of a heatsink from the semiconductor package. other embodiments are described and claimed.
20250112483. TECHNIQUES TO ENABLE SMART BATTERY CHARGING_simplified_abstract_(intel corporation)
Inventor(s): Naoki Matsumura of San Jose CA US for intel corporation, Ajit Kadaveru of Fairfax VA US for intel corporation, Jagadish Singh of Bangalore IN for intel corporation
IPC Code(s): H02J7/00, G01R31/392
CPC Code(s): H02J7/0069
Abstract: embodiments herein relate to techniques to facilitate a user to enable one or more smart battery charging algorithms on a device to control charging of a battery associated with the device. a control circuitry of the device may receive usage data associated with a battery of the device (e.g., via a battery interface). the control circuitry may predict a future health metric of the battery based on the usage data. the control circuitry may compare the future metric to a threshold and trigger, based on the comparison, display of information about one or more smart charging algorithms to the user. additionally, or alternatively, the control circuitry may generate predicted performance information associated with multiple charging configurations and present the performance information to the user. other embodiments may be described and claimed.
20250112603. WIDEBAND CHANNEL SELECTIVE AMPLIFIER STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Ashoke RAVI of Portland OR US for intel corporation, Ofir DEGANI of Haifa IL for intel corporation, Sashank KRISHNAMURTHY of Hillsboro OR US for intel corporation, Soumya GUPTA of Corvallis OR US for intel corporation
IPC Code(s): H03F3/45, H03F1/02, H03F1/22
CPC Code(s): H03F3/45192
Abstract: an amplifier structure may include a first amplifier substructure having a first amplifier and a first filter structure and provide a first high frequency output signal and a first low frequency output signal having a frequency lower than a frequency of the first high frequency output signal. it may include a second amplifier substructure having a second amplifier and a second filter structure and provide a second high frequency output signal and a second low frequency output signal having a frequency lower than the frequency of the second high frequency output signal. it may include a first combination node configured to receive the first high frequency output signal and the second low frequency output signal and to provide a first amplified signal, and a second combination node configured to receive the first low frequency output signal and the second high frequency output signal and to provide a second amplified signal.
Inventor(s): Susnata MONDAL of Hillsboro OR US for intel corporation, Mozhgan MANSURI of Portland OR US for intel corporation
IPC Code(s): H03H11/02, G06F1/08, G06F1/10
CPC Code(s): H03H11/02
Abstract: disclosed are multi-phase coupled resonant clock generation circuits that include magnetic coupling compensation techniques. also disclosed are resonant distribution circuits that can use inductors spaced more closely to one another.
Inventor(s): Eli BOROKHOVICH of Modiin-Maccabim-Reut IL for intel corporation, Assaf BEN-BASSAT of Haifa IL for intel corporation
IPC Code(s): H04B1/00, H04B1/04, H04B1/408
CPC Code(s): H04B1/0078
Abstract: a transmitter comprises a first amplifier coupled to a first modulated local oscillator signal and a second amplifier coupled to a second modulated local oscillator signal. digital to time conversion circuitry is configured to generate the first modulated local oscillator signal and the second modulated local oscillator signal such that the second modulated local oscillator signal has a delay to the first modulated local oscillator signal.
20250112659. METHODS AND DEVICES TO PERFORM SPECTRUM SENSING_simplified_abstract_(intel corporation)
Inventor(s): Wayne BALLANTYNE of Chandler AZ US for intel corporation, David GRAHAM of Gilbert AZ US for intel corporation, Markus Dominik MUECK of Unterhaching DE for intel corporation, Zoran ZIVKOVIC of Hertogenbosch NL for intel corporation
IPC Code(s): H04B1/16
CPC Code(s): H04B1/16
Abstract: disclosed herein is an apparatus of a radio communication device, where the apparatus may include a plurality of signal paths, each signal path of the plurality of signal paths is configured to receive a radio frequency, rf, signal from a corresponding rf circuit. the apparatus may also include a processor configured to determine first signal paths and a second signal path from the plurality of signal paths, wherein the first signal paths are configured to receive first rf signals of the rf signals. the processor may also be configured to demodulate the first rf signals received from the first signal paths to decode received communication data; perform, for a frequency band, an rf environmental sensing operation based on a digital signal converted from a second rf signal of the rf signals, wherein the second rf signal is provided by the second signal path.
Inventor(s): Horaira ABU of Fremont CA US for intel corporation, Harry MULJONO of San Ramon CA US for intel corporation, Gerald S. PASDAST of San Jose CA US for intel corporation
IPC Code(s): H04B1/38, H03K5/1252
CPC Code(s): H04B1/38
Abstract: in some embodiments, an interconnect with a plurality of single-ended, bi-directional channels capable of simultaneous bi-directional data transfer is provided. there may be tx/rx circuits, each having a suppression circuit, on each side of a channel with each being capable of operating at independent supply levels and clock frequencies.
20250112675. EIGHT PORT UPLINK TRANSMISSION ENHANCEMENTS_simplified_abstract_(intel corporation)
Inventor(s): Guotong Wang of Beijing CN for intel corporation, Alexei Davydov of Nizhny Novgorod RU for intel corporation
IPC Code(s): H04B7/0456, H04L27/26, H04W72/21
CPC Code(s): H04B7/0456
Abstract: an apparatus and system of providing uplink transmission with eight ports are described. precoders for partial and full coherent ue uplink transmissions are described, in addition to downlink control information (dci) enhancements and sounding reference signal (srs) configurations for codebook-based uplink transmission. precoder matrices are provided for different ranks for the eight port transmissions.
20250112698. MULTI-FIBER CABLE CONNECTIVITY_simplified_abstract_(intel corporation)
Inventor(s): Kartik LAKHOTIA of San Jose CA US for intel corporation, Fabrizio PETRINI of Menlo Park CA US for intel corporation
IPC Code(s): H04B10/25, H04Q11/00
CPC Code(s): H04B10/25
Abstract: examples described herein relate to a network configured according to a topology, where the network is to provide communication between the first computing device and the second computing device. in some examples, the network includes a combination of a connected shuffle box or a bipartite shuffle box. various examples of connected shuffle boxes and bipartite shuffle boxes are described herein.
20250112756. SECURING AUDIO COMMUNICATIONS_simplified_abstract_(intel corporation)
Inventor(s): Pradeep M. Pappachan of Tualatin OR US for intel corporation, Reshma Lal of Portland OR US for intel corporation, Rakesh A. Ughreja of Bangalore IN for intel corporation, Kumar N. Dwarakanath of Folsom CA US for intel corporation, Victoria C. Moore of Phoenix AZ US for intel corporation
IPC Code(s): H04L9/00, G06F9/54, G06F21/44, G06F21/57, G06F21/60, G06F21/83, G06F21/84, H04L9/08, H04L9/40
CPC Code(s): H04L9/00
Abstract: systems and methods include establishing a cryptographically secure communication between an application module and an audio module. the application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. the establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.
Inventor(s): Raghavan KUMAR of Hillsboro OR US for intel corporation, Sanu K. MATHEW of Portland OR US for intel corporation, Adish VARTAK of Palo Alto CA US for intel corporation, Christopher B. WILKERSON of Vancouver WA US for intel corporation
IPC Code(s): H04L9/00, H04L9/06
CPC Code(s): H04L9/008
Abstract: examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (fhe) workload. examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.
Inventor(s): David M. Durham of Beaverton OR US for intel corporation, Christoph Dobraunig of St. Veit an der Glan AT for intel corporation
IPC Code(s): H04L9/06
CPC Code(s): H04L9/0643
Abstract: techniques for preventing replay for compressible data are described. in certain examples, a computing system includes a memory; an execution circuitry to execute an instruction to generate a memory request to read a data line from the memory; and a memory controller circuit to: determine that a field of the data line is not set to a conflict indicator value, determine that the field of the data line is set to a compressed indicator value, in response to the determinations, perform a hash of a compressed data field of the data line using a key to generate a tag, compare the tag generated by the hash to a corresponding tag field of the data line, and decompress the compressed data field of the data line, in response to the tag generated by the hash matching the corresponding tag field of the data line, to generate decompressed data.
Inventor(s): Dan Horovitz of Rishon Letzion IL for intel corporation, Liron Ain-Kedem of Kiryat Tivon IL for intel corporation, Guy Ben-Artzi of Zichron Yaacov IL for intel corporation
IPC Code(s): H04L9/14, H04L9/08, H04L9/32
CPC Code(s): H04L9/14
Abstract: disclosed examples generate an original equipment manufacturer (oem) private key and an oem public key; generate an oem certificate based on the oem public key; cause sending of the oem certificate from an oem product to a silicon provider, the silicon provider to sign the oem certificate based on a silicon provider private key; and cause storage of the signed oem certificate in the oem product.
Inventor(s): Sachin TANEJA of Hillsboro OR US for intel corporation, Sanu K. MATHEW of Portland OR US for intel corporation, Christopher B. WILKERSON of Vancouver WA US for intel corporation, Raghavan KUMAR of Hillsboro OR US for intel corporation, Anupam GOLDER of Hillsboro OR US for intel corporation
IPC Code(s): H04L9/30, H04L9/00, H04L9/08
CPC Code(s): H04L9/3093
Abstract: bandwidth of high bandwidth memory (hbm) and scratch pad memory used by an fully homomorphic encryption (fhe) accelerator in a system-on-chip (soc) during fhe relinearization is reduced by including a key generator module in the soc. the key generator module to generate fhe public keys from a seed that is input to the soc. the seed used by the on-die key generator module to generate fhe relinearization public keys locally within the scratch pad memory units in the soc.
Inventor(s): Santosh GHOSH of Hillsboro OR US for intel corporation, Manoj SASTRY of Portland OR US for intel corporation
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3247
Abstract: a digital signature verification unit or other apparatus of an aspect includes cryptographic hash circuitry to generate cryptographic hashes and multi-scheme hash-based digital signature verification circuitry coupled with the cryptographic hash circuitry. the multi-scheme hash-based digital signature verification circuitry is to use the cryptographic hash circuitry to verify digital signatures according to only one of a plurality of hash-based digital signature verification schemes at a time, the plurality of hash-based digital signature verification schemes including a first hash-based digital signature verification scheme and a second hash-based digital signature verification scheme. other apparatus, methods, and systems are disclosed.
Inventor(s): Francesc Guim Bernat of Barcelona ES for intel corporation, Kshitij Arun Doshi of Tempe AZ US for intel corporation, Ned M. Smith of Beaverton OR US for intel corporation
IPC Code(s): H04L41/084, G06F1/20, G06F9/48, G06F9/50, G06F9/54, G06F11/30, H04L9/06, H04L9/32, H04L41/0869, H04L41/5054, H04L47/78, H04L49/00, H04L67/10, H04W4/08, H04W12/04
CPC Code(s): H04L41/0843
Abstract: various aspects of methods, systems, and use cases for multi-entity (e.g., multi-tenant) edge computing deployments are disclosed. among other examples, various configurations and features enable the management of resources (e.g., controlling and orchestrating hardware, acceleration, network, processing resource usage), security (e.g., secure execution and communication, isolation, conflicts), and service management (e.g., orchestration, connectivity, workload coordination), in edge computing deployments, such as by a plurality of edge nodes of an edge computing environment configured for executing workloads from among multiple tenants.
Inventor(s): Hossein FARROKHBAKHT of Toronto CA for intel corporation, Kartik LAKHOTIA of San Jose CA US for intel corporation, Fabrizio PETRINI of Menlo Park CA US for intel corporation
IPC Code(s): H04L47/12, H04L5/00, H04L47/11, H04L47/17
CPC Code(s): H04L47/12
Abstract: examples described herein relate to switch circuitry that is to: detect congestion based on information and based on detection of the congestion, perform a congestion mitigation action. in some examples, detect congestion based on the information includes: access a first value that indicates a number of packets received at a first input port and to be egressed from an output port of the multiple output ports, access a second value that indicates a number of packets received at a second input port and to be egressed from the output port, and generate the information based on the first value and the second value.
Inventor(s): Min Suet Lim of Gelugor MY for intel corporation, Eng Huat Goh of Ayer Itam MY for intel corporation, Tin Poay Chuah of Bayan Lepas MY for intel corporation, Kavitha Nagarajan of Bangalore IN for intel corporation, Telesphor Kamgaing of Chandler AZ US for intel corporation, Poh Boon Khoo of Bayan Lepas MY for intel corporation, Jiun Hann Sir of Gelugor MY for intel corporation
IPC Code(s): H05K1/02, H05K1/11, H05K1/18, H05K3/34, H05K3/40
CPC Code(s): H05K1/0216
Abstract: technologies for a shield for electromagnetic interference include a circuit board with an integrated circuit package on it, with a hole in the circuit board under the integrated circuit package. the integrated circuit package may include one or more dies or other components on the underside of the package, at least partially positioned in the hole in the circuit board. an electromagnetic shield box can be positioned in the hole. tabs of the electromagnetic shield box may interface with pads on the same side of the circuit board as the integrated circuit package. the electromagnetic shield box may prevent or reduce electromagnetic or radiofrequency interference on the components of the integrated circuit package. positioning the electromagnetic shield box can reduce the overall height of the circuit board, among other advantages.
Inventor(s): Venkata Mahesh Gunnam of Andhra Pradesh IN for intel corporation, Rakesh Yedri of Bangalore IN for intel corporation, Phani Alaparthi of Bangalore IN for intel corporation, David Elayaraj Samaraj of Natrampalli IN for intel corporation, Jackson C.P. Kong of Tanjung Tokong MY for intel corporation, Bala Subramanya of Bangalore IN for intel corporation, Navneet Kumar Singh of Bangalore IN for intel corporation, Yagnesh V. Waghela of Bangalore IN for intel corporation
IPC Code(s): H05K1/02, H05K3/12, H05K3/34
CPC Code(s): H05K1/0219
Abstract: technologies for reducing the impact of inductors on electrical traces are disclosed. in an illustrative embodiment, conductive ink is applied in a silk screen layer on top of a solder mask of a circuit board. the conductive ink forms shield regions under and near where inductors are placed and/or where a power plane is routed. the conductive shield regions may be coupled to a ground plane in the circuit board. the conductive shield regions can partially shield traces under and near the inductor, reducing the noise induced on nearby traces. the conductive shield regions can allow traces for high-speed input/output signals to be routed closer to the inductor, reducing the size, number of layers, and/or cost of the circuit board. in some embodiments, the conductive shield regions can shield emissions from the power plane, reducing interference on antennas of a device.
Inventor(s): Bai NIE of Chandler AZ US for intel corporation, Mitchell PAGE of Mesa AZ US for intel corporation, Junxin WANG of Gilbert AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Haifa HARIRI of Phoenix AZ US for intel corporation, Nicholas S. HAEHN of Scottsdale AZ US for intel corporation, Astitva TRIPATHI of Mesa AZ US for intel corporation, Yuqin LI of Chandler AZ US for intel corporation, Hongxia FENG of Chandler AZ US for intel corporation, Haobo CHEN of Chandler AZ US for intel corporation, Bohan SHAN of Chandler AZ US for intel corporation, Hiroki TANAKA of Gilbert AZ US for intel corporation, Leonel R. ARANA of Phoenix AZ US for intel corporation, Yonggang Yong LI of Chandler AZ US for intel corporation
IPC Code(s): H05K1/02, H01L23/15, H01L23/498, H05K1/03, H05K1/11
CPC Code(s): H05K1/0271
Abstract: embodiments disclosed herein include package substrates with a glass core. in an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. in an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. in an embodiment a corner at a junction between the sidewall and the first surface is rounded. in an embodiment, a via is provided in the opening, where the via is electrically conductive.
Inventor(s): Jeff Ku of Taipei TW for intel corporation, Smit Kapila of Bangalore IN for intel corporation, Min Suet Lim of Gelugor MY for intel corporation, Surya Pratap Mishra of Portland IN for intel corporation, Kari Mansukoski of Hillsboro OR US for intel corporation, Shantanu D. Kulkarni of Hillsboro OR US for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20154
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for foldable thermal ground planes for electronic devices. an example an apparatus to cool an electronic device includes a first plate; a second plate; a plurality of first pillars extending between the first plate and the second plate, the plurality of first pillars having a first shape; a plurality of second pillars extending between the first plate and the second plate, the plurality of second pillars having a second shape, the second shape different than the first shape; and a hinge separating the apparatus into a first section and a second section, the plurality of second pillars in the hinge.
Inventor(s): Bernardo MORA VILLALOBOS of Alajuela CR for intel corporation, Alonso RODRIGUEZ CHACON of La Guacima CR for intel corporation
IPC Code(s): H05K9/00
CPC Code(s): H05K9/0016
Abstract: a shielding structure and method for assembling a shielding structure for an electronic component. the shielding structure includes a core comprising an elastic material and at least a spring part of the core comprising an arch. the structure further includes an electromagnetic interference (emi) shielding material affixed to the core. the method for producing the shielding structure includes forming a core comprising an elastic material, wherein the core includes at least a spring part comprising one or more arches. the method further includes covering at least a part of the core in an emi shielding material.
Inventor(s): Nicolas Butzen of Portland OR US for intel corporation, Harish K. Krishnamurthy of Beaverton OR US for intel corporation, Khondker Ahmed of Hillsboro OR US for intel corporation, Nachiket Desai of Portland OR US for intel corporation, Su Hwan Kim of Portland OR US for intel corporation, Krishnan Ravichandran of Saratoga CA US for intel corporation, Kaladhar Radhakrishnan of Chandler AZ US for intel corporation, Jonathan Douglas of Cave Creek AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H10D1/68
Abstract: embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (ic) package. the voltage regulator may provide a power supply to one or more load domains in the ic package. the transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the ic package. the capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. other embodiments may be described and claimed.
Inventor(s): Kiran Chikkadi of Hillsboro OR US for intel corporation, Michael L. Hattendorf of Portland OR US for intel corporation, Darshil Gala of Milpitas CA US for intel corporation, Maheshwar Ghimire of Hillsboro OR US for intel corporation, Ryan Wood of Beaverton OR US for intel corporation
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/78
CPC Code(s): H10D30/024
Abstract: an integrated circuit (ic) device includes a transistor channel region within (and over a base of) a semiconductor fin, a gate structure over the fin, an isolation or dielectric material adjacent the base of the fin, and an intervening spacer material adjacent the fin, over the dielectric material, and between the channel region (and gate structure) and the isolation or dielectric material. the intervening spacer material may be at substantially equal heights on both sides of the fin. the intervening spacer material may have a height or thickness that is substantial portion of the height of the fin. the spacer and isolation materials may be on both sides of the fin, and between the fin and adjacent fins.
20250113520. TRANSFER OF A 2D MATERIAL TO A TARGET SUBSTRATE_simplified_abstract_(intel corporation)
Inventor(s): Andrey Vyatskikh of Hillsboro OR US for intel corporation, Paul Fischer of Portland OR US for intel corporation, Paul Nordeen of Portland OR US for intel corporation, Kevin O'Brien of Portland OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation, Carl H. Naylor of Portland OR US for intel corporation, Uygar Avci of Portland OR US for intel corporation
IPC Code(s): H01L29/775, H01L21/762
CPC Code(s): H10D30/43
Abstract: techniques and mechanisms for a transition metal dichalcogenide (tmd) material to be grown on one structure, and then transferred to a different structure. in an embodiment, one or more monolayers of a tmd material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. a material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. the resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. the ablation enables the substrate to be separated from the one or more monolayers. in an embodiment, a residue on a surface of the one or more tmd monolayers is an artefact of the layer transfer process.
Inventor(s): Andrey Vyatskikh of Hillsboro OR US for intel corporation, Paul B. Fischer of Portland OR US for intel corporation, Paul Killian Nordeen of Portland OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Mahmut Sami Kavrik of Eugene OR US for intel corporation, Ande Kitamura of Portland OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Carl Hugo Naylor of Portland OR US for intel corporation, Kevin P. O'Brien of Portland OR US for intel corporation
IPC Code(s): H01L29/775, H01L21/762
CPC Code(s): H10D30/43
Abstract: a transition metal dichalcogenide (tmd) monolayer grown on a growth substrate is directly transferred to a target substrate. eliminating the use of a carrier wafer in the tmd monolayer transfer process reduces the number of transfers endured by the tmd monolayer from two to one, which can result in less damage to the tmd monolayer. after a tmd monolayer is grown on a growth layer, a protective layer is formed on the tmd monolayer. the protective layer is bonded to the target substrate by a diffusion bonding layer. the direct transfer of tmd monolayers can be repeated to create a stack of tmd monolayers. a stack of tmd monolayers can be used in a field effect transistor, such as a nanoribbon field effect transistor.
20250113529. INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS_simplified_abstract_(intel corporation)
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Jessica PANELLA of Banks OR US for intel corporation, Manjunath CHINNAPPAMUDALIAR RAJAGOPAL of Hillsboro OR US for intel corporation, SHARANYA SUBRAMANIAM of Beaverton OR US for intel corporation, Robert JOACHIM of Beaverton OR US for intel corporation, Dario FARIAS of Portland OR US for intel corporation
IPC Code(s): H01L29/78, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D30/6211
Abstract: integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. for example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. a first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing. a first isolation structure is overlying the end of the first fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the first gate structure, and a second isolation structure is overlying the end of the second fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the second gate structure.
Inventor(s): Carl H. Naylor of Portland OR US for intel corporation, Rachel Steinhardt of Santa Clara CA US for intel corporation, Mahmut Sami Kavrik of Eugene OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Kevin O’Brien of Portland OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Ashish Verma Penumatcha of Beaverton OR US for intel corporation, Uygar Avci of Portland OR US for intel corporation, Matthew Metz of Portland OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation
IPC Code(s): H01L29/49, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/76, H01L29/775, H01L29/786
CPC Code(s): H10D30/6739
Abstract: techniques and mechanisms for providing gate dielectric structures of a transistor. in an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (tmd) material. the channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. a composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. the composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. in another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.
Inventor(s): Chia-Ching LIN of Portland OR US for intel corporation, Tao CHU of Portland OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Guowei XU of Portland OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Feng ZHANG of Hillsboro OR US for intel corporation, Yue ZHONG of Portland OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Kevin P. O’BRIEN of Portland OR US for intel corporation, Uygar E. AVCI of Portland OR US for intel corporation, Carl H. NAYLOR of Portland OR US for intel corporation, Mahmut Sami KAVRIK of Eugene OR US for intel corporation, Andrey VYATSKIKH of Hillsboro OR US for intel corporation, Rachel STEINHARDT of Beaverton OR US for intel corporation, Chelsey DOROW of Portland OR US for intel corporation, Kirby MAXEY of Hillsboro OR US for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/24, H01L29/417, H01L29/66, H01L29/775
CPC Code(s): H10D30/6757
Abstract: integrated circuit structures having internal spacers for 2d channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2d channel materials, are described. for example, an integrated circuit structure includes a stack of two-dimensional (2d) material nanowires. a gate structure is vertically around the stack of 2d material nanowires. internal gate spacers are between vertically adjacent ones of the stack of 2d material nanowires and laterally adjacent to the gate structure. the 2d material nanowires are recessed relative to the internal gate spacers. conductive contact structures are at corresponding ends of the stack of 2d material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.
Inventor(s): Glenn GLASS of Portland OR US for intel corporation, Anand MURTHY of Portland OR US for intel corporation, Biswajeet GUHA of Hillsboro OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation, Susmita GHOSE of Hillsboro OR US for intel corporation, Zachary GEIGER of Hillsboro OR US for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/08, H01L29/423
CPC Code(s): H10D30/6757
Abstract: gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. for example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. a vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. a gate stack is around the vertical arrangement of horizontal silicon nanowires. a first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.
20250113559. TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER_simplified_abstract_(intel corporation)
Inventor(s): Guowei XU of Portland OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Feng ZHANG of Hillsboro OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Tao CHU of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Chung-Hsun LIN of Portland OR US for intel corporation, Oleg GOLONZKA of Beaverton OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Chia-Ching LIN of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H10D62/115
Abstract: trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. in an example, an integrated circuit structure includes a fin structure. an epitaxial source or drain structure is on the fin structure. an isolation structure is laterally adjacent to sides of the fin structure. a dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. a conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. the conductive trench contact structure does not extend into the isolation structure.
Inventor(s): Rahul Ramaswamy of Portland OR US for intel corporation, Marko Radosavljevic of Portland OR US for intel corporation, Hsu-Yu Chang of Hillsboro OR US for intel corporation, Scott M. Mokler of Hillsboro OR US for intel corporation, Stephanie Chin of Portland OR US for intel corporation, Walid M. Hafez of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L27/092, H01L29/423, H01L29/778, H01L29/78, H01L29/786
CPC Code(s): H10D62/116
Abstract: in stacked transistor device, such as a complementary field-effect-transistor (cfet) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the pmos layer, and a compressive material is deposited in second isolation region in the nmos layer. the strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. in some cases, in one or both of the isolation regions, a liner material is included between the strain material and the source and drain regions. certain embodiments provide independent tuning of strain forces in a stacked transistor device. different materials are selected for different layers in the stacked device to provide favorable performance enhancement or tuning (e.g., adjustment of the threshold voltage) in nmos and pmos layers.
Inventor(s): Leonard Guler of Hillsboro OR US for intel corporation, Saurabh Acharya of Beaverton OR US for intel corporation, Nidhi Khandelwal of Portland OR US for intel corporation, Prabhjot Kaur Luthra of Hillsboro OR US for intel corporation, Sean Pursel of Tigard OR US for intel corporation, Izabela Anna Samek of Hillsboro OR US for intel corporation
IPC Code(s): H01L29/06, H01L27/088, H01L29/417, H01L29/423, H01L29/78
CPC Code(s): H10D62/119
Abstract: in one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. the second transistor device is spaced a first distance laterally from the first transistor device. the structure further includes a dielectric region between the first gate stack and the second gate stack. the dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.
Inventor(s): Leonard Guler of Hillsboro OR US for intel corporation, Charles H. Wallace of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/311, H01L21/762, H01L29/66, H01L29/786
CPC Code(s): H10D62/121
Abstract: an integrated circuit (ic) device has a stack of nanoribbons between epitaxial source and drain structures with first and second dielectric sections separated by a dielectric layer and adjacent an epitaxial structure. a second dielectric layer may separate a third dielectric section. the dielectric layers may be conformally between the epitaxial structure and the dielectric sections. a height at a top of the epitaxial structure may be reduced, for example, to be very close to a height at a top of the stack of nanoribbons, e.g., within a pitch or thickness of the nanoribbons.
Inventor(s): Mahmut Sami Kavrik of Hillsboro OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Kevi P. Obrien of Portland OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Carl H. Naylor of Portland OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Scott B. Clendenning of Portland OR US for intel corporation, Matthew Metz of Portland OR US for intel corporation, Marko Radosavljevic of Portlan OR US for intel corporation
IPC Code(s): H01L29/18, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/84
Abstract: techniques and mechanisms for forming a gate dielectric structure and source or drain (s/d) structures on a monolayer channel structure of a transistor. in an embodiment, the channel structure comprises a two-dimensional (2d) layer of a transition metal dichalcogenide (tmd) material. during fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. while a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (s/d) electrode structure that adjoins the first portion. in another embodiment, the dielectric material is an oxide of a group v-vi transition metal.
Inventor(s): Andrey Vyatskikh of Hillsboro OR US for intel corporation, Paul B. Fischer of Portland OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation, Mahmut Sami Kavrik of Eugene OR US for intel corporation, Karthik Krishnaswamy of Portland OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Jennifer Lux of Hillsboro OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Carl Hugo Naylor of Portland OR US for intel corporation, Kevin P. O'Brien of Portland OR US for intel corporation, Justin R. Weber of Beaverton OR US for intel corporation
IPC Code(s): H01L29/18, H01L21/02, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/778, H01L29/78
CPC Code(s): H10D62/84
Abstract: a low strain transfer protective layer is formed on a transition metal dichalcogenide (tmd) monolayer to enable the transfer of the tmd monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the tmd monolayer. transfer of a tmd monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. transfer of the tmd monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the tmd monolayer from the growth substrate. the low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the tmd monolayer during lift-off. the carrier wafer and protective layer are separated from the tmd monolayer after attachment of the tmd monolayer to the target substrate.
Inventor(s): Leonard Guler of Hillsboro OR US for intel corporation, Shaun Mills of Hillsboro OR US for intel corporation, Joseph D'Silva of Hillsboro OR US for intel corporation, Ehren Mannebach of Beaverton OR US for intel corporation, Mauro Kobrinsky of Portland OR US for intel corporation, Charles H. Wallace of Portland OR US for intel corporation, Kalpesh Mahajan of Portland OR US for intel corporation, Vivek Vishwakarma of Vancouver WA US for intel corporation, Dincer Unluer of Hillsboro OR US for intel corporation, Jessica Panella of Banks OR US for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/256
Abstract: devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. a first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. a second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.
20250113581. TRENCH CONTACT STRUCTURE WITH AIRGAP SPACER_simplified_abstract_(intel corporation)
Inventor(s): Hwichan JUN of Portland OR US for intel corporation, Guillaume BOUCHE of Portland OR US for intel corporation, Sudipto NASKAR of Portland OR US for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H10D64/258
Abstract: trench contact structures with airgap spacers, and methods of fabricating trench contact structures with airgap spacers, are described. in an example, an integrated circuit structure includes a fin structure or a nanowire structure. an epitaxial source or drain structure is on the fin structure or the nanowire structure. a gate structure is over the fin structure or around the nanowire structure. a trench contact structure is laterally spaced apart from the gate structure and coupled to the epitaxial source or drain structure. a trench contact spacer is adjacent to sidewalls of the trench contact structure, the trench contact spacer including an outer spacer portion, an airgap, and an inner spacer portion.
Inventor(s): Rahul PANDEY of Hillsboro OR US for intel corporation, Yang CAO of Beaverton OR US for intel corporation, Rahul RAMAMURTHY of Hillsboro OR US for intel corporation, Jubin NATHAWAT of Hillsboro OR US for intel corporation, Michael L. HATTENDORF of Portland OR US for intel corporation, Jae HUR of Hillsboro OR US for intel corporation, Anant H. JAHAGIRDAR of Portland OR US for intel corporation, Steven R. NOVAK of Portland OR US for intel corporation, Tao CHU of Portland OR US for intel corporation, Yanbin LUO of Portland OR US for intel corporation, Minwoo JANG of Portland OR US for intel corporation, Paul A. PACKAN of Hillsboro OR US for intel corporation, Owen Y. LOH of Portland OR US for intel corporation, David J. TOWNER of Portland OR US for intel corporation
IPC Code(s): H01L29/51, H01L21/3115, H01L29/40, H01L29/78
CPC Code(s): H10D64/683
Abstract: an integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. a multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. a gate electrode is over and on a topmost material in the multilayer high-k gate stack. fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.
Inventor(s): Tao CHU of Portland OR US for intel corporation, Minwoo JANG of Portland OR US for intel corporation, Yanbin LUO of Portland OR US for intel corporation, Paul PACKAN of Hillsboro OR US for intel corporation, Guowei XU of Portland OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Feng ZHANG of Hillsboro OR US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Chia-Ching LIN of Portland OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Chung-Hsun LIN of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D84/834
Abstract: multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. for example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. a second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. an n-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. a p-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the p-type gate structure in contact with the n-type gate structure with a pn boundary between the p-type gate structure and the n-type gate structure. the pn boundary is offset from a central location between the first fin structure or vertical arrangement of horizontal nanowires and the second fin structure or vertical arrangement of horizontal nanowires.
Inventor(s): Dan Lavric of Portland OR US for intel corporation, Jubin Nathawat of Hillsboro OR US for intel corporation, Orb Acton of Portland OR US for intel corporation, Michal Mleczko of Portland OR US for intel corporation, Owen Loh of Portland OR US for intel corporation, Michael L. Hattendorf of Portland OR US for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/20, H01L29/423, H01L29/51
CPC Code(s): H10D84/85
Abstract: an integrated circuit (ic) device includes n- and p-type transistors with and without threshold voltage shifts using a common dopant material in a gate dielectric. the ic device includes at least four threshold voltage for each of n- and p-type transistors. besides volumeless doping of gate dielectrics, work function metals are used in both n- and p-type transistors. a single dipole dopant may be concurrently introduced into and through similar gate dielectrics in both n- and p-type transistors to achieve consistent threshold voltage shifts with minimal process variation.
Inventor(s): Rachel A. Steinhardt of Beaverton OR US for intel corporation, Kevin P. O'Brien of Portland OR US for intel corporation, Ashish Verma Penumatcha of Hillsboro OR US for intel corporation, Carl Hugo Naylor of Portland OR US for intel corporation, Kirby Maxey of Hillsboro OR US for intel corporation, Pratyush P. Buragohain of Hillsboro OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation, Mahmut Sami Kavrik of Eugene OR US for intel corporation, Wouter Mortelmans of Portland OR US for intel corporation, Marko Radosavljevic of Portland OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Matthew V. Metz of Portland OR US for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/26, H01L29/66, H01L29/775
CPC Code(s): H10D84/85
Abstract: methods for doping 2d transistor devices and resulting architectures. the use and placement of oxide dopants, such as, but not limited to, geox, enable control over threshold voltage performance and contact resistance of 2d transistor devices. architectures include distinct stoichiometry compositions.
Inventor(s): Yulia Gotlib of Hillsboro OR US for intel corporation, Matthew J. Prince of Portland OR US for intel corporation, Sachin S. Vaidya of Portland OR US for intel corporation, Ying Zhou of Portland OR US for intel corporation, Xiaoye Qin of Portland OR US for intel corporation, Ryan Pearce of Beaverton OR US for intel corporation, Andrew Arnold of Hillsboro OR US for intel corporation, Chiao-Ti Huang of Portland OR US for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D84/85
Abstract: techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. a semiconductor device includes a gate structure around or otherwise on a semiconductor region. the gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. in an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of si—h bonds compared to si—n bonds at an interface between the dielectric liner and the gate structure. the liner may also include a higher percentage of si—n bonds compared to si—h bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.
Inventor(s): Munzarin QAYYUM of Hillsboro OR US for intel corporation, Rohit GALATAGE of Portland OR US for intel corporation, Marko RADOSAVLJEVIC of Portland OR US for intel corporation, Cheng-Ying HUANG of Portland OR US for intel corporation, Evan CLINTON of Carrollton GA US for intel corporation, David BENNETT of Portland OR US for intel corporation, Jami WIEDEMER of Scappoose OR US for intel corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D84/856
Abstract: gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating depopulated channel structures using split source or drain approaches, are described. for example, an integrated circuit structure includes a first vertical arrangement of nanowires, the first vertical arrangement of nanowires having one or more dielectric nanowires coupled to a dielectric source or drain structure. a first gate stack is over the first vertical arrangement of nanowires. a second vertical arrangement of nanowires is laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure laterally spaced apart from the dielectric source or drain structure. a second gate stack is over the second vertical arrangement of nanowires.
Inventor(s): Martin D. GILES of Portland OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation
IPC Code(s): H01L27/12, H01L21/02, H01L21/8238, H01L21/84, H01L27/092, H01L29/165, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D86/215
Abstract: methods are disclosed for forming fins in transistors. in one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.
- INTEL CORPORATION
- B23K26/40
- B23K26/53
- B23K101/40
- B23K103/00
- CPC B23K26/40
- Intel corporation
- C08F20/18
- C08F22/10
- C09J133/10
- CPC C08F20/18
- G01L1/24
- CPC G01L1/24
- G01R31/28
- G01K1/22
- G01K1/26
- CPC G01R31/287
- G01R31/319
- G01R31/317
- G01R31/3185
- CPC G01R31/31917
- G01S7/41
- G01S7/35
- G01S13/931
- CPC G01S7/411
- G02B6/12
- CPC G02B6/12002
- G02B6/36
- CPC G02B6/3652
- G02B6/38
- CPC G02B6/3881
- G02B6/42
- CPC G02B6/4226
- C09J171/02
- CPC G02B6/4239
- H01L23/00
- H01L23/367
- H01L25/16
- H01L25/18
- CPC G02B6/4274
- G03F7/11
- G03F7/20
- G03F7/38
- CPC G03F7/11
- G05D1/02
- G06T15/08
- G06T17/00
- G06V20/50
- G06V20/70
- CPC G05D1/0274
- G06F1/324
- G06F1/3234
- CPC G06F1/324
- G06F9/30
- G06F9/38
- G06T15/00
- CPC G06F9/30025
- G06F15/80
- CPC G06F9/30076
- CPC G06F9/30145
- CPC G06F9/3016
- G06F9/54
- CPC G06F9/544
- CPC G06F9/546
- G06F11/34
- CPC G06F11/3409
- G06F12/0811
- CPC G06F12/0811
- G06F12/0831
- G06F12/0846
- CPC G06F12/0831
- G06F13/28
- CPC G06F13/28
- G06F13/40
- G06F12/1072
- G06F13/16
- G06F13/42
- G06F15/167
- CPC G06F13/404
- G06F15/78
- CPC G06F15/7839
- G06F17/15
- G06F12/0875
- G06N3/04
- G06N3/063
- CPC G06F17/153
- G06F30/31
- CPC G06F30/31
- G06F30/327
- CPC G06F30/327
- G06F30/34
- CPC G06F30/34
- G06N3/0464
- G06N3/08
- CPC G06N3/0464
- G06T1/60
- G06T15/06
- CPC G06T15/005
- G06T15/50
- G06T1/20
- G06T3/40
- CPC G06T15/506
- H01L21/02
- H01L23/48
- H01L29/10
- H01L29/423
- CPC H01L21/02178
- H01L21/67
- H01L21/56
- H01L21/683
- H01L21/762
- CPC H01L21/67288
- H01L23/538
- CPC H01L21/6835
- H01L21/768
- H01L23/498
- H01L25/065
- CPC H01L21/76224
- H01L23/29
- H01L23/31
- H01L25/00
- CPC H01L23/291
- H01L25/10
- CPC H01L23/367
- H01L23/373
- C22C26/00
- CPC H01L23/3732
- H01L27/092
- H01L29/06
- H01L29/775
- H01L29/786
- CPC H01L23/481
- H01L23/528
- H01L29/18
- H01L29/78
- H01L23/482
- CPC H01L23/4821
- H01L23/495
- H01L21/48
- CPC H01L23/49513
- H01L23/15
- CPC H01L23/49822
- CPC H01L23/49827
- CPC H01L23/49838
- H05K1/02
- H05K1/03
- H05K1/11
- CPC H01L23/49894
- H01L23/522
- H01L23/532
- CPC H01L23/5226
- H01L27/06
- CPC H01L23/5227
- H01L23/544
- H01L27/088
- H01L29/417
- CPC H01L23/528
- CPC H01L23/5286
- CPC H01L23/53214
- CPC H01L23/53238
- H10B80/00
- CPC H01L23/5381
- CPC H01L23/5383
- CPC H01L23/5384
- CPC H01L23/5385
- G03F7/09
- H01L23/58
- CPC H01L23/544
- CPC H01L23/562
- H01L21/3205
- H01L23/13
- H01L21/8234
- CPC H01L23/564
- H01L23/64
- H01F17/00
- H01F17/06
- CPC H01L23/645
- CPC H01L24/05
- CPC H01L24/08
- CPC H01L24/14
- CPC H01L24/16
- H01L23/38
- H01L23/433
- H10N19/00
- CPC H01L24/32
- CPC H01L24/73
- CPC H01L24/80
- CPC H01L25/0652
- G06F12/0897
- H01L23/053
- CPC H01L25/0655
- H01L21/8238
- CPC H01L25/0657
- CPC H01L25/18
- H01L25/075
- CPC H01L25/50
- H01Q1/22
- H01Q1/48
- H01Q5/40
- H01Q9/04
- CPC H01Q1/2283
- H01Q5/385
- H01Q1/38
- H01Q1/50
- H01Q21/28
- CPC H01Q5/385
- H01R12/85
- CPC H01R12/85
- H02J7/00
- G01R31/392
- CPC H02J7/0069
- H03F3/45
- H03F1/02
- H03F1/22
- CPC H03F3/45192
- H03H11/02
- G06F1/08
- G06F1/10
- CPC H03H11/02
- H04B1/00
- H04B1/04
- H04B1/408
- CPC H04B1/0078
- H04B1/16
- CPC H04B1/16
- H04B1/38
- H03K5/1252
- CPC H04B1/38
- H04B7/0456
- H04L27/26
- H04W72/21
- CPC H04B7/0456
- H04B10/25
- H04Q11/00
- CPC H04B10/25
- H04L9/00
- G06F21/44
- G06F21/57
- G06F21/60
- G06F21/83
- G06F21/84
- H04L9/08
- H04L9/40
- CPC H04L9/00
- H04L9/06
- CPC H04L9/008
- CPC H04L9/0643
- H04L9/14
- H04L9/32
- CPC H04L9/14
- H04L9/30
- CPC H04L9/3093
- CPC H04L9/3247
- H04L41/084
- G06F1/20
- G06F9/48
- G06F9/50
- G06F11/30
- H04L41/0869
- H04L41/5054
- H04L47/78
- H04L49/00
- H04L67/10
- H04W4/08
- H04W12/04
- CPC H04L41/0843
- H04L47/12
- H04L5/00
- H04L47/11
- H04L47/17
- CPC H04L47/12
- H05K1/18
- H05K3/34
- H05K3/40
- CPC H05K1/0216
- H05K3/12
- CPC H05K1/0219
- CPC H05K1/0271
- H05K7/20
- CPC H05K7/20154
- H05K9/00
- CPC H05K9/0016
- CPC H10D1/68
- H01L29/66
- CPC H10D30/024
- CPC H10D30/43
- CPC H10D30/6211
- H01L29/49
- H01L29/24
- H01L29/76
- CPC H10D30/6739
- CPC H10D30/6757
- H01L29/08
- CPC H10D62/115
- H01L29/778
- CPC H10D62/116
- CPC H10D62/119
- H01L21/311
- CPC H10D62/121
- CPC H10D62/84
- CPC H10D64/256
- CPC H10D64/258
- H01L29/51
- H01L21/3115
- H01L29/40
- CPC H10D64/683
- CPC H10D84/834
- H01L29/20
- CPC H10D84/85
- H01L29/26
- H01L21/822
- CPC H10D84/856
- H01L27/12
- H01L21/84
- H01L29/165
- CPC H10D86/215