INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications published on December 14th, 2023

Patent applications for INTERNATIONAL BUSINESS MACHINES CORPORATION on December 14th, 2023

LANDSCAPE CHANNELING USING AN AUTONOMOUS ROBOTIC SOIL DREDGER (17806740)

Main Inventor

Partho Ghosh

Brief explanation

The abstract describes a computer-based method for using an autonomous robotic soil dredger to dynamically shape landscapes. The method involves analyzing various landscape metrics, such as soil quality, environmental conditions, and vegetation water consumption. Based on these metrics, a digital representation of proposed trench and ridge metrics is generated, including trench depth, distance between trenches, stream size, trench slope, and shape. A trench pattern is then determined based on this digital representation, and the autonomous robotic soil dredger is used to create the trenches according to the pattern.

• Computer-based method for shaping landscapes using an autonomous robotic soil dredger
• Derives landscape metrics including soil quality, environmental conditions, and vegetation water consumption
• Generates a digital twin of proposed trench and ridge metrics based on the derived landscape metrics
• Proposed metrics include trench depth, distance between trenches, stream size, trench slope, and shape
• Determines a trench pattern based on the digital twin
• Collaborates with the autonomous robotic soil dredger to create the trenches according to the pattern

Potential Applications

• Landscaping and land management projects
• Agricultural irrigation systems
• Erosion control and flood prevention measures
• Environmental restoration and conservation efforts

Problems Solved

• Efficient and precise shaping of landscapes
• Optimization of trench and ridge metrics for desired outcomes
• Reduction of manual labor and human error in landscape channeling
• Adaptation to changing environmental conditions and soil quality

Benefits

• Increased efficiency and accuracy in landscape channeling
• Improved water management and conservation
• Enhanced erosion control and flood prevention
• Facilitation of environmental restoration and conservation efforts

Abstract

A computer-implemented method for dynamic landscape channeling using an autonomous robotic soil dredger. The method derives one or more landscape metrics, wherein the one or more landscape metrics comprise soil metrics, environmental conditions, and vegetation water consumption metrics. The method further generates a digital twin of proposed trench and ridge metrics based on the derived one or more landscape metrics, wherein the proposed trench and ridge metrics comprise a depth of the trench, a distance between one or more trenches, a stream size, a slope of the trench, and a shape of the trench. The method further determines a trench pattern based on the generated digital twin of the proposed trench and ridge metrics and collaborates with the autonomous robotic soil dredger to generate the trench pattern.

MULTI-AXIS MAGNETIC FIELD VECTOR GENERATION (17806590)

Main Inventor

Oki GUNAWAN

Brief explanation

The abstract of this patent application describes a method, system, and computer program product for configuring dipole-line (DL) magnets to generate a specific magnetic field vector. The method involves obtaining the configuration of DL magnets and selecting the desired magnetic field vector. Based on the configuration, the orientations of the DL magnets are determined to generate the specified magnetic field vector.

• The patent application is for a method, system, and computer program product related to configuring dipole-line (DL) magnets.
• The method involves obtaining the configuration of DL magnets and selecting a magnetic field vector to be generated.
• Based on the configuration, the orientations of the DL magnets are determined to generate the specified magnetic field vector.

Potential Applications

This technology has potential applications in various fields, including:

• Magnetic resonance imaging (MRI) systems
• Particle accelerators
• Magnetic confinement fusion devices
• Magnetic sensors and detectors

Problems Solved

The technology described in this patent application addresses the following problems:

• Efficiently configuring dipole-line (DL) magnets to generate a specific magnetic field vector
• Determining the orientations of DL magnets based on their configuration to achieve the desired magnetic field vector

Benefits

The technology offers several benefits, including:

• Improved accuracy and precision in generating specific magnetic field vectors
• Enhanced efficiency in configuring DL magnets for various applications
• Potential for improved performance and functionality of magnetic systems

Abstract

A method, system, and computer program product are disclosed. The method includes obtaining a configuration of dipole-line (DL) magnets and selecting a magnetic field vector to be generated. The method also includes determining, based on the configuration, orientations of the DL magnets for generating the magnetic field vector.

DYNAMICALLY ALTERING A CODE EXECUTION WORKFLOW DURING DEVELOPMENT USING AUGMENTED REALITY (17806520)

Main Inventor

Michael Boone

Brief explanation

The abstract describes a computer-implemented method for dynamically altering a code execution workflow using augmented reality (AR). Here are the key points:

• The method involves receiving virtual modifications of a source code from an AR device.
• The user can virtually alter the source code on the AR device.
• Based on the virtually altered source code, an altered execution workflow is generated.
• The altered execution workflow is overlaid on the AR device.
• The altered execution workflow is executed in response to a user request for testing the virtually altered source code.
• The result of executing the altered execution workflow is displayed on the AR device.
• If the user provides satisfactory feedback about the result, the source code is physically altered according to the virtually altered source code.

Potential Applications:

• Software development: This technology can be used by developers to quickly test and modify code in an immersive AR environment, improving the efficiency of the development process.
• Code debugging: Debugging code can be made more intuitive and interactive by allowing developers to virtually alter the code and see the immediate effects in the AR environment.
• Collaborative coding: Multiple developers can use AR devices to virtually modify and test code together, enhancing collaboration and productivity.

Problems Solved:

• Traditional code testing and modification processes can be time-consuming and require switching between different tools and environments. This technology streamlines the process by allowing virtual modifications and testing in a single AR environment.
• Debugging code can be challenging, especially when trying to understand the impact of changes. AR provides a visual and interactive way to see the effects of code alterations in real-time.

Benefits:

• Improved efficiency: The ability to virtually modify and test code in an AR environment reduces the time and effort required for code development and debugging.
• Enhanced collaboration: AR devices enable multiple developers to work together on code modifications, improving teamwork and productivity.
• Intuitive debugging: Visualizing code alterations in an AR environment makes it easier to identify and fix issues, leading to more effective debugging.

Abstract

A computer-implemented method, a computer program product, and a computer system for dynamically altering a code execution workflow using augmented reality (AR). A computer receives, from an AR device of a user, virtual modification of a source code, where the user virtually alters the source code on the augmented realty device. A computer generates an altered execution workflow, based on a virtually altered source code created in the virtual modification. A computer overlays the altered execution workflow on the AR device. A computer executes the altered execution workflow, in response to receiving from the AR device a user request for testing the virtually altered source code. A computer displays on the augmented realty device a result of executing the altered execution workflow. A computer physically alters the source code according to the virtually altered source code, in response to receiving from the AR device satisfactory user feedback about the result.

CONTAINER IMAGE OPTIMIZATION FOR A SELECTED DEPLOYMENT ENVIRONMENT (17806320)

Main Inventor

Ashok Pon Kumar Sree Prakash

Brief explanation

The patent application describes a method for optimizing container images in a deployment environment. Here are the key points:

• The method involves obtaining a list of container images to be deployed in a computing environment to provide various services.
• The total layer size of the container images is determined based on the size of individual image layers.
• At least one container image is reconfigured to adjust the total layer size of the deployment.
• The reconfiguration is based on deployment characteristics and involves replacing image layers with other layers configured based on the other container images in the deployment.

Potential Applications

• Cloud computing platforms
• Microservices architectures
• Container orchestration systems

Problems Solved

• Inefficient use of resources due to large container image sizes
• Slow deployment and scaling of containerized applications
• Increased storage requirements for container images

Benefits

• Optimized container images result in reduced storage requirements and faster deployment times.
• Efficient use of resources leads to cost savings and improved performance.
• Simplified management and scaling of containerized applications.

Abstract

Container image optimization is provided for a deployment environment. An indication of a plurality of container images to be deployed in a deployment to provide a plurality of services within a computing environment is obtained. The plurality of container images of the deployment has a total layer size of a plurality of image layers of the plurality of container images. At least one container image of the plurality of container images is reconfigured to adjust the total layer size for the deployment. The reconfiguring is based on one or more deployment characteristics of the deployment and includes replacing at least one image layer of a container image of the at least one container image with one or more other image layers configured based on the plurality of container images to be deployed.

GENERATING COMPLIANT CONTAINER IMAGES VIA EMBEDDINGS (17806739)

Main Inventor

Ashok Pon Kumar Sree Prakash

Brief explanation

The abstract describes a method, computer systems, and program product for importing non-compliant container images. Here is a simplified explanation of the abstract:

• The method involves receiving a non-compliant container image that does not meet the requirements of a target computing environment.
• The image is then processed to extract one or more embeddings, which are representations of the image's content.
• These embeddings are compared to a collection of embeddings from an image catalog.
• Based on this comparison, a similar image from the catalog is identified.
• Finally, the similar image is deployed in the target computing environment.

Potential Applications

• Importing non-compliant container images into a target computing environment.
• Ensuring compatibility of container images with specific computing environments.

Problems Solved

• Importing non-compliant container images that do not meet the requirements of a target computing environment.
• Finding suitable alternative container images that are compatible with the target environment.

Benefits

• Enables the use of non-compliant container images by finding similar images that are compliant.
• Simplifies the process of importing container images into specific computing environments.
• Reduces the risk of compatibility issues and improves overall system stability.

Abstract

A method, computer systems and program product to import non-compliant container images is provided. A processor receives a non-compliant container image, wherein the container image is not compliant with a target computing environment. A processor extracts a one or more embeddings from the non-compliant container image. A processor compares the one or more embeddings from the non-compliant container image to a plurality of one or more embeddings from an image catalog. A processor identifies a similar image from the image catalog based on the comparison of layer embeddings from the non-compliant container image and the similar image. A processor deploys the similar image in the target computing environment.

MODULAR DECOMPOSITION AND COMPOSITION OF CONTAINER SOFTWARE MANAGEMENT CLUSTERS IN HYBRID CLOUD (17806615)

Main Inventor

Vishal Anand

Brief explanation

The abstract describes a method for replicating a software cluster in a different computing environment. This involves generating software operators based on the functionalities of the control software cluster, analyzing the code and configurations of the cluster, and determining software configuration requirements. A template for the control software cluster is created based on these requirements and the analysis of the new computing environment. The software operators can then be replicated in the new environment.

• Software operators are generated based on the functionalities of the control software cluster.
• Code and configurations of the control software cluster are analyzed to derive the software operators.
• Software configuration requirements for the control software cluster are determined.
• A template for the control software cluster is created based on the determined requirements and the analysis of the new computing environment.
• The software operators of the control software cluster can be replicated in the new computing environment.

Potential Applications

• Replicating complex software clusters in different computing environments.
• Streamlining the process of setting up and configuring software clusters.
• Enabling easy migration of software clusters to new environments.

Problems Solved

• Replicating software clusters can be a complex and time-consuming task.
• Ensuring that the replicated cluster functions properly in the new environment can be challenging.
• Configuring software clusters to meet specific requirements can be difficult and error-prone.

Benefits

• Simplifies the process of replicating software clusters.
• Reduces the time and effort required to set up and configure software clusters.
• Improves the reliability and consistency of replicated software clusters.
• Enables efficient migration of software clusters to different computing environments.

Abstract

Replicating a software cluster which includes control software and containers in another computing environment can include software operators which can be generated relating to modular functionalities of a control software cluster. The software operators are derived from analyzing the control software cluster. The software operators further being derived from analyzing code of the control software cluster including the containers, and from analyzing software configurations for the control software cluster. The generating of the software operators can include, at least in part, determining software configuration requirements for the control software cluster. The generating of the software operators including at least in part, creating a template for the control software cluster based on the determined software configuration requirements and the analysis of the another software computing environment. All or a portion of the software operators of the control software cluster can be replicated in the another software computing environment.

PROVISIONAL RESOURCE SCHEDULING IN A CLOUD COMPUTING ENVIRONMENT (18062182)

Main Inventor

Asser Nasreldin Tantawi

Brief explanation

The patent application describes an approach for scheduling resources in a cloud computing environment. Here are the key points:

• The approach involves receiving a request to host an application, which includes virtual units with topological constraints.
• Resources are scheduled for each virtual unit, taking into account the topological constraints and assigning a weight to each resource.
• If a second request is received, the resources are re-allocated to virtual units of the second request based on their topological constraints and weights, with the goal of minimizing the total weight.
• Each resource is then assigned a new weight.

Potential applications of this technology:

• Cloud computing providers can use this approach to efficiently allocate resources to different applications and virtual units.
• It can be applied in various industries where cloud computing is used, such as e-commerce, healthcare, and finance.

Problems solved by this technology:

• Provisional scheduling of resources in a cloud computing environment can be complex and time-consuming. This approach simplifies the process by considering topological constraints and weights.
• It minimizes the total weight of resources, leading to more efficient resource allocation and utilization.

Benefits of this technology:

• Improved resource allocation: By considering topological constraints and weights, the approach ensures that resources are allocated in a way that optimizes their utilization.
• Time and cost savings: The provisional scheduling and re-allocation process is automated, reducing the time and effort required for resource management.
• Enhanced performance: By minimizing the total weight of resources, the approach helps to improve the overall performance and efficiency of applications hosted in the cloud computing environment.

Abstract

Approaches presented herein enable provisional scheduling of resources in a cloud computing environment. More specifically, a first group request to host an application is obtained. This first group request includes one or more virtual units, which each have one or more topological constraints. One or more resources are scheduled for each of the virtual units. This scheduling includes provisionally allocating the resources to each of the virtual units according to the topological constraints. Each resource comprises a respective weight. In response to obtaining a second group request, the resources are provisionally re-allocated to one or more virtual units of the second group request according to one or more topological constraints of the second group request and the respective weight of each of the resources. This re-allocating minimizes a summation of each respective weight of the resources. A new respective weight is then assigned to each of the resources.

COMPUTER-BASED SERVICE CHAIN NODE ADEQUACY FRAMEWORK (17806201)

Main Inventor

Harish Bharti

Brief explanation

The patent application describes a method to improve the efficiency of service chain nodes in a network using 5G technology. The method involves creating network slices for specific business processes to ensure stable operations of each node.

• Utilizes 5G technology standard for broadband cellular networks architecture
• Creates network slices for dedicated business processes
• Ensures stable operations of each node within the network slice
• Optimizes network adequacy to handle requests
• Introduces a model for pre-processor without impacting existing functionality
• Balances queues and implements rapid packet delivery to decongested queues

Potential Applications

• Telecommunication networks
• Internet of Things (IoT) networks
• Cloud computing networks
• Service providers and data centers

Problems Solved

• Inefficient service chain node operations
• Congestion and delays in network queues
• Inadequate network capacity to handle requests

Benefits

• Improved efficiency and stability of service chain nodes
• Faster packet delivery and reduced congestion
• Enhanced network capacity and performance
• Better utilization of 5G technology for dedicated business processes

Abstract

In an approach to improve service chain node adequacy, embodiments utilize fifth-generation technology standard (5G) for broadband cellular networks architecture for creating relevant network slices for dedicated business processes, to ensure that each node within the network slice has stabilized operations. Embodiments employ an optimization technique, maximize a model of network adequacy to ensure there is a predetermined amount of adequacy to handle a request, and introduce the model for pre-processor without impacting existing functionality. Embodiments apply one or more constraints to one or more systems to balance the one or more queues; and implement a rapid packet delivery to a subsequent entity comprising decongested queues.

TRANSLATION SUPPORT FOR A VIRTUAL CACHE (18452310)

Main Inventor

Markus Helms

Brief explanation

The abstract describes a virtual cache and method in a processor that supports multiple threads on the same cache line. The processor is designed to support virtual memory and multiple threads. The virtual cache directory consists of multiple directory entries, each associated with a cache line. Each cache line has a tag that includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread accessing the cache line. When a new thread determines that the cache line is valid for that thread, the validity bit for that thread is set without affecting the validity bits for other threads.

• The invention is a virtual cache and method in a processor that enables multiple threads to access the same cache line.
• The processor is capable of supporting virtual memory and multiple threads simultaneously.
• The virtual cache directory contains multiple directory entries, each corresponding to a cache line.
• Each cache line has a tag that includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread accessing the cache line.
• When a new thread accesses the cache line, it checks the validity bit for that thread and sets it if the cache line is valid for that thread.
• The validity bits for other threads remain unaffected, allowing multiple threads to access the same cache line simultaneously.

Potential Applications

• This technology can be applied in processors that support virtual memory and multiple threads.
• It can enhance the performance and efficiency of multi-threaded applications by allowing multiple threads to access the same cache line without invalidating each other's data.

Problems Solved

• The technology solves the problem of efficiently managing cache lines in processors that support virtual memory and multiple threads.
• It allows multiple threads to access the same cache line without invalidating each other's data, improving performance and reducing cache misses.

Benefits

• Improved performance and efficiency of multi-threaded applications.
• Reduced cache misses and improved cache utilization.
• Enhanced support for virtual memory and multiple threads in processors.

Abstract

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Domain-Agnostic Natural Language Processing Using Explainable Interpretation Feedback Models (17804143)

Main Inventor

YAZAN OBEIDI

Brief explanation

The abstract describes a natural language processing system that can process queries and provide explainable interpretations. Here are the key points:

• The system receives a natural language query.
• It automatically detects if the query has implicit intent.
• If implicit intent is detected, the system generates a modified query with a default inference from a fact sheet.
• The modified query is presented to the user, who is asked for feedback.
• If the modified query is approved, a final output is generated.
• If the modified query is rejected, the system generates an alternative inference and presents a further modified query to the user.

Potential applications of this technology:

• Customer service chatbots that can understand and interpret user queries.
• Virtual assistants that can provide explanations for their responses.
• Information retrieval systems that can generate more accurate queries based on user feedback.

Problems solved by this technology:

• Ambiguity in natural language queries can be resolved by generating default inferences.
• Users can provide feedback to improve the accuracy of the system's interpretations.
• The system can provide explainable outputs, increasing user trust and understanding.

Benefits of this technology:

• Improved accuracy in understanding and interpreting natural language queries.
• User feedback helps in refining the system's interpretations.
• Explainable outputs enhance user trust and satisfaction.

Abstract

An embodiment including a domain-agnostic natural language processing system for processing natural language queries having an explainable interpretation feedback model is provided. The embodiment may include receiving a natural language query. The embodiment may also include to automatically detecting whether the received natural language query includes implicit intent therein. The embodiment may include, in response to detecting implicit intent in the received natural language query, automatically generating a modified query including a default inference from an interpretation fact sheet. The embodiment may further include automatically presenting the modified query to the user and asking the user for feedback on the modified query. The embodiment may also include automatically generating a final output if the modified query was approved, or automatically determining an alternative inference and presenting a further modified query including the alternative inference to the user if the modified query was rejected.

DATABASE COMPRESSION ORIENTED TO COMBINATIONS OF RECORD FIELDS (17806359)

Main Inventor

Ying Zhang

Brief explanation

This patent application describes a method, system, and computer program for compressing databases by optimizing the storage of combinations of fields within a database record. Here are the key points:

• The technology focuses on identifying combinations of fields within a database record that have higher access frequencies than a predetermined threshold.
• Once these combinations are determined, the record is reorganized to store the fields of each combination in a contiguous storage space.
• The reorganized record is then compressed using a compression scheme specifically designed for the identified combinations of fields.

Potential applications of this technology:

• Database management systems: This innovation can be implemented in various database management systems to improve storage efficiency and optimize access to frequently accessed combinations of fields.
• Big data analytics: As the volume of data continues to grow, efficient database compression techniques can enhance the performance of big data analytics platforms by reducing storage requirements and improving data retrieval speeds.

Problems solved by this technology:

• Inefficient storage: Traditional database storage methods may not effectively utilize storage space, leading to wasted resources and slower data access.
• Slow data retrieval: Without optimized storage and compression techniques, accessing specific combinations of fields within a database record can be time-consuming, especially when dealing with large datasets.

Benefits of this technology:

• Improved storage efficiency: By identifying and organizing frequently accessed combinations of fields, this technology reduces the overall storage footprint of a database, resulting in cost savings and improved resource utilization.
• Faster data retrieval: Storing related fields in contiguous storage spaces allows for quicker access to specific combinations of fields, enhancing the overall performance of database queries and data retrieval operations.

Abstract

This disclosure provides a computer-implemented method, a computer system and a computer program product for database compression oriented to combinations of fields of a database record. One or more combinations of fields of a record of a database are determined that satisfy a frequency criterion indicating that access frequencies of the one or more combinations of fields are higher than an access frequency threshold. The record is reorganized based on the one or more combinations of fields to store fields of each combination of the one or more combinations of fields in a respective contiguous storage space. The reorganized record is compressed by applying a compression scheme to the one or more combinations of fields.

QUERY OPTIMIZATION USING REINFORCEMENT LEARNING (17931588)

Main Inventor

Thomas A. Beavin

Brief explanation

The abstract describes a computer-implemented method for improving query performance in a database management system (DBMS). Here are the key points:

• The method involves a query optimizer in the DBMS receiving a query for execution.
• The query optimizer creates an initial access path for the query based on the current state of the system.
• The query is executed based on the initial access path.
• A query agent in the DBMS observes the execution of the query.
• The query agent determines if a change to the initial access path would improve the query's execution.
• If a change is deemed beneficial, the query agent modifies at least one aspect of the state to improve the query's performance.

Potential applications of this technology:

• Database management systems that handle large volumes of queries and data.
• Systems that require efficient query execution for improved performance.
• Any application that relies on a DBMS and wants to optimize query performance.

Problems solved by this technology:

• Slow query performance in a DBMS.
• Inefficient access paths chosen by the query optimizer.
• Lack of real-time optimization during query execution.

Benefits of this technology:

• Improved query performance and execution speed.
• Real-time optimization based on observed query execution.
• Enhanced efficiency and effectiveness of the query optimizer in a DBMS.

Abstract

According to an aspect, a computer-implemented method for improving query performance in a databased management system (DBMS) includes receiving, by a query optimizer of the DMBS, a query for execution. The method also includes creating, by the query optimizer, an initial access path for the query based on state and executing the query based on the initial access path. The method further includes observing, by a query agent of the DBMS, the execution of the query and modifying at least one of the state based on a determination by the query agent that a change to the initial access path would improve the execution of the query.

AUTOMATED FACT CHECKING USING ITERATIVE KNOWLEDGE BASE QUERYING (17747463)

Main Inventor

G P Shrivatsa Bhargav

Brief explanation

The patent application describes a method for decomposing a natural language assertion into a question and answer pair. This involves translating the question into a structured knowledge graph query and performing an iterative process of querying the knowledge graph and evaluating the responses.

• The method decomposes a natural language assertion into a question and answer pair.
• It translates the question into a structured knowledge graph query.
• The method performs an iterative process of querying the knowledge graph and evaluating the responses.
• In each iteration, the method retrieves a predicted answer and checks its similarity with the initial answer.
• If the similarity does not meet a threshold criterion, the query is altered and used for the next iteration.
• The method also generates an assertion correctness score based on the confidence scores obtained during the iterative process.

Potential Applications

• Natural language processing systems
• Question-answering systems
• Knowledge graph-based search engines

Problems Solved

• Difficulty in decomposing natural language assertions into question and answer pairs
• Inefficient querying of knowledge graphs for accurate answers
• Lack of confidence scoring for factual assertions

Benefits

• Improved accuracy in decomposing natural language assertions
• Efficient querying of knowledge graphs for accurate answers
• Confidence scoring to assess the correctness of assertions

Abstract

An embodiment includes decomposing a natural language assertion into a natural language question and answer pair that includes an initial question and an initial answer. The embodiment translates the initial question into a structured knowledge graph query and then performs an iterative process comprising iterative querying of a knowledge graph and evaluating of corresponding query responses resulting in respective confidence scores. A first iteration of the iterative process comprises querying of the knowledge graph to retrieve a first predicted answer, then determining whether a degree of similarity between the initial answer and the first predicted answer meets a threshold criterion. If not, the first predicted query is altered and used for querying the knowledge graph in a subsequent iteration of the iterative process. The embodiment also generates an assertion correctness score indicative of a degree of confidence that the assertion is factual using the respective confidence scores.

COOPERATIVE BUILD AND CONTENT ANNOTATION FOR CONVERSATIONAL DESIGN OF VIRTUAL ASSISTANTS (17806559)

Main Inventor

Muhtar Burak Akbulut

Brief explanation

The abstract of this patent application describes a system for cooperative design of virtual assistants. Here are the key points:

• The system uses a processor to analyze the user's build activity and create a build context.
• The processor then generates content queries based on the build context.
• A content index is created by combining a text-search index with a neural Information Retrieval (IR) index.
• The content index is searched using the content queries to find relevant content.
• The processor applies heuristic rules to the build context and identified content to generate recommendations for the user.
• These recommendations can be build suggestions or content annotation suggestions.

Potential Applications

This technology could be applied in various areas, including:

• Virtual assistant design: The system can help designers and developers in creating conversational virtual assistants by providing relevant content and build suggestions.
• Content annotation: The system can assist in annotating content for virtual assistants, making it easier to organize and retrieve information.

Problems Solved

The system addresses the following problems:

• Lack of relevant content: By searching a content index using build context, the system ensures that the identified content is relevant to the user's needs.
• Designing virtual assistants: The system provides build suggestions and content annotation suggestions, helping designers and developers in the conversational design process.

Benefits

The benefits of this technology include:

• Improved efficiency: The system automates the process of finding relevant content and generating recommendations, saving time and effort for designers and developers.
• Enhanced user experience: By providing relevant content and suggestions, the system helps in creating more effective and user-friendly virtual assistants.
• Collaborative design: The system enables cooperative design by incorporating user build activity and generating recommendations based on it.

Abstract

In an approach for a cooperative build and content annotation system for conversational design of virtual assistants, a processor formulates a build context based on a build activity of a user. A processor formulates one or more content queries based on the build context. A processor builds a content index by augmenting a text-search index with a neural Information Retrieval (IR) index. A processor searches the content index using the one or more content queries to identify content relevant to the build context. A processor determines at least one recommendation for the user based on heuristic rules applied to the build context and the identified content, wherein each recommendation is a build suggestion or a content annotation suggestion.

PROTECTING SENSITIVE DATA DUMP INFORMATION (17839346)

Main Inventor

Xi Bo Zhu

Brief explanation

The abstract describes a method and system for protecting sensitive data dump information. Here is a simplified explanation of the abstract:

• The method involves using a processor to receive a dump file associated with an application.
• User classification profiles are created to define security access levels to different regions of the dump file.
• A first encrypted region, which is a subset of the different regions, is encrypted using a first encryption key associated with a specific user classification profile.
• The encrypted dump file is then produced.
• The method also involves determining a user who belongs to the specific user classification profile and providing them with access to the encrypted dump file and a decryption key to decrypt the first encrypted region.

Potential applications of this technology:

• Data protection in applications that deal with sensitive information.
• Secure storage and transfer of sensitive data dump files.
• Access control and encryption for different user classification profiles.

Problems solved by this technology:

• Protecting sensitive data dump information from unauthorized access.
• Ensuring that only users with the appropriate security access levels can access specific regions of the dump file.
• Providing a secure method for decrypting encrypted regions of the dump file.

Benefits of this technology:

• Enhanced security and protection of sensitive data.
• Efficient access control for different user classification profiles.
• Simplified encryption and decryption process for specific regions of the dump file.

Abstract

A method and implementing system protects sensitive data dump information. The method comprises using a processor receiving a dump file (DF) associated with an application. The method further comprises allocating user classification profiles defining security access levels to different regions of the DF and encrypting a first encrypted region that is a proper subset of the different regions using a first encryption key associated with a first user classification profile of the user classification profiles to produce an encrypted DF (EDF). The method further comprises determining a first user to be a member of the first user classification profile, and providing access to the EDF and a first decryption key useable to decrypt the first encrypted region to the first user.

NEURAL CAPACITANCE: NEURAL NETWORK SELECTION VIA EDGE DYNAMICS (17838722)

Main Inventor

Pin-Yu Chen

Brief explanation

The abstract describes a method for modifying a pre-trained neural network model by incorporating a neural capacitance probe unit on top of one or more bottom layers. The probe unit is randomly initialized and the modified model is trained by fine-tuning the bottom layers on a target dataset. The method involves obtaining an adjacency matrix from the initialized probe unit and computing a neural capacitance metric using this matrix. An active model is selected based on this metric and a machine learning system is configured using the active model.

• The method modifies a pre-trained neural network model by adding a neural capacitance probe unit on top of one or more bottom layers.
• The probe unit is randomly initialized and the modified model is trained by fine-tuning the bottom layers on a target dataset.
• An adjacency matrix is obtained from the initialized probe unit and a neural capacitance metric is computed using this matrix.
• An active model is selected based on the neural capacitance metric.
• A machine learning system is configured using the selected active model.

Potential Applications

• This method can be applied in various fields where neural networks are used, such as computer vision, natural language processing, and speech recognition.
• It can be used to improve the performance and accuracy of pre-trained neural network models in specific tasks or domains.

Problems Solved

• The method solves the problem of modifying pre-trained neural network models to adapt them to specific tasks or datasets.
• It addresses the challenge of incorporating additional layers or units on top of existing neural network architectures without losing the knowledge learned by the pre-trained model.

Benefits

• The method allows for the modification and fine-tuning of pre-trained neural network models, saving time and computational resources compared to training from scratch.
• It enables the customization of neural network models for specific tasks or datasets, improving their performance and accuracy.
• The use of the neural capacitance metric helps in selecting the most suitable modified model, ensuring optimal performance for the target task.

Abstract

An output layer is removed from a pre-trained neural network model and a neural capacitance probe unit with multiple layers is incorporated on top of one or more bottom layers of the pre-trained neural network model. The neural capacitance probe unit is randomly initialized and a modified neural network model is trained by fine-tuning the one or more bottom layers on a target dataset for a maximum number of epochs, the modified neural network model comprising the neural capacitance probe unit incorporated with multiple layers on top of the one or more bottom layers of the pre-trained neural network model. An adjacency matrix is obtained from the initialized neural capacitance probe unit and a neural capacitance metric is computed using the adjacency matrix. An active model is selected using the neural capacitance metric and a machine learning system is configured using the active model.

REASONING WITH REAL-VALUED FIRST ORDER LOGIC AND PROBABILITY INTERVALS (17806019)

Main Inventor

Radu MARINESCU

Brief explanation

The patent application describes a method for improving routing in a computing system using a processor. Here are the key points:

• The method converts all first-order logic formulas into real-valued logic formulas.
• It executes a probabilistic inference using the real-valued logic formulas and probability intervals associated with atomic formulas in a knowledge base.
• The result is an interval conditional probability that indicates the likelihood of a first predicate condition being true based on the truth of one or more alternative predicates.

Potential applications of this technology:

• Enhanced routing in computer networks
• Intelligent decision-making systems
• Natural language processing and understanding
• Machine learning algorithms

Problems solved by this technology:

• Inefficient routing in computing systems
• Difficulty in handling complex logic formulas
• Lack of probabilistic reasoning in traditional routing algorithms

Benefits of this technology:

• Improved accuracy and efficiency in routing decisions
• Enhanced ability to handle complex logic and probabilistic reasoning
• Better decision-making capabilities in various applications

Abstract

Embodiments are provided for providing enhanced routing in a computing system by a processor. All first-order logic formulas may be converted into real-valued logic formulas. A probabilistic inference is executed using the real-valued logic formulas and one or more probability intervals associated with an atomic formulae in a knowledge base to provide an interval conditional probability indicating that a first predicate condition is true based one or more alternative predicates being true.

INTERPRETABLE NEURAL NETWORK ARCHITECTURE USING CONTINUED FRACTIONS (17806188)

Main Inventor

Isha Puri

Brief explanation

The abstract describes a method, neural network, and computer program product for training neural networks using continued fractions architectures. The method involves inputting data into the neural network and training it through multiple layers to generate output data. Each layer calculates linear functions of its input and generates an output for the subsequent layer.

• The method involves training neural networks with continued fractions architectures.
• Input data is provided to each layer along with output data from the previous layer.
• Each layer calculates linear functions of its input and generates an output for the subsequent layer.
• The neural network outputs the final output data.

Potential Applications

• This technology can be applied in various fields where neural networks are used, such as image recognition, natural language processing, and financial forecasting.
• It can enhance the performance and accuracy of neural networks in these applications.

Problems Solved

• Continued fractions architectures provide a new approach to training neural networks.
• This method allows for more efficient and effective training of neural networks.
• It addresses the challenge of improving the performance and accuracy of neural networks.

Benefits

• The use of continued fractions architectures can lead to improved performance and accuracy of neural networks.
• Training neural networks with this method can result in faster convergence and better generalization.
• It provides a novel approach to training neural networks, expanding the possibilities for their application.

Abstract

A method, a neural network, and a computer program product are provided that provide training of neural networks with continued fractions architectures. The method includes receiving, as input to a neural network, input data and training the input data through a plurality of continued fractions layers of the neural network to generate output data. The input data is provided to each of the continued fractions layers as well as output data from a previous layer. The method further includes outputting, from the neural network, the output data. Each continued fractions layer of the continued fractions layers is configured to calculate one or more linear functions of its respective input and to generate an output that is used as the input for a subsequent continued fractions layer, each continued fractions layer configured to generate an output that is used as the input for a subsequent layer.

VERTICAL FEDERATED LEARNING WITH SECURE AGGREGATION (17838445)

Main Inventor

Shiqiang Wang

Brief explanation

The patent application describes a method for analyzing the connections between layers of a neural network model used for vertical federated learning. The method involves generating an undirected graph of nodes, where nodes with multiple child nodes perform aggregation operations. The model's output corresponds to a node in the graph. 

• The method analyzes the model to identify a layer where the sum of lower layer outputs is computed.
• This identified layer is then partitioned into two parts: one part is applied to multiple entities, and the other part acts as an aggregator for the outputs of the first part.
• Aggregation operations are performed between pairs of lower layer outputs.
• Multiple forward and backward passes of the neural network model are executed, incorporating secure aggregation and maintaining the model's partitioning.

Potential Applications

• Vertical federated learning: The method is specifically designed for vertical federated learning, where multiple entities collaborate to train a shared model without sharing their private data.
• Privacy-preserving machine learning: By performing secure aggregation and maintaining model partitioning, the method ensures privacy protection during the training process.
• Collaborative AI: The method enables multiple entities to contribute to the training of a neural network model while preserving data privacy.

Problems Solved

• Privacy concerns in federated learning: The method addresses the challenge of training a shared model without exposing sensitive data from individual entities.
• Efficient aggregation in distributed learning: By partitioning the model and performing aggregation operations, the method optimizes the aggregation process in a distributed learning setting.

Benefits

• Enhanced privacy: The method incorporates secure aggregation and maintains model partitioning, ensuring that sensitive data remains private during the training process.
• Improved collaboration: Multiple entities can contribute to the training of a shared model, enabling collaborative learning without compromising data privacy.
• Efficient distributed learning: By partitioning the model and performing aggregation operations, the method optimizes the training process in a distributed learning environment.

Abstract

The method provides for analyzing input and output connections of layers of a received neural network model configured for vertical federated learning. An undirected graph of nodes is generated in which a node having two or more child nodes includes an aggregation operation, based on the analysis of the model in which a model output corresponds to a node of the graph. A layer of the model is identified in which a sum of lower layer outputs are computed. The identified model layer is partitioned into a first part applied respectively to the multiple entities and a second part applied as an aggregator of the output of the first part. The aggregation operation is performed between pairs of lower layer outputs, and multiple forward and backward passes of the neural network model are performed that include secure aggregation and maintain model partitioning in forward and backward passes.

DATA FACET GENERATION AND RECOMMENDATION (17806530)

Main Inventor

Manjit Singh Sodhi

Brief explanation

The abstract describes a method, computer program, and computer system for generating data facets and transformations for a dataset. Here are the key points:

• Data associated with a dataset is received, which includes data entries with elements and data types.
• Data facets are generated for each data entry based on the associated data type.
• Transformations are generated for the data facets based on a machine learning task associated with the dataset.
• A recommendation is provided to the user, including computer code for an optimal transformation.

Potential Applications

This technology has potential applications in various fields, including:

• Data analysis and exploration
• Machine learning and predictive modeling
• Natural language processing and text mining
• Image and video processing
• Sensor data processing

Problems Solved

This technology addresses the following problems:

• Manual and time-consuming process of generating data facets and transformations for a dataset.
• Difficulty in identifying optimal transformations for a specific machine learning task.
• Lack of automated recommendations for data analysis and modeling tasks.

Benefits

The use of this technology offers several benefits:

• Automation of the data facet and transformation generation process, saving time and effort.
• Improved accuracy and efficiency in identifying relevant data facets and transformations.
• Enhanced performance and effectiveness of machine learning tasks.
• Facilitates data analysis and modeling tasks for users with limited programming or data science expertise.

Abstract

A method, computer program, and computer system are provided for data facet generation. Data associated with a dataset is received. The received data includes one or more data entries having one or more elements. The one or more elements are associated with one or more data types. One or more data facets are generated for each of the data entries with the received data based on the associated data type. One or more transformations are generated for the data facet corresponding to a machine learning task associated with the dataset. A recommendation is provided to a user based on the generated transformation. The provided recommendation includes generated computer code corresponding to an optimal transformation associated with the machine learning task.

PREDICTING DEVICE INSULATION CONDITION AND PROVIDING OPTIMAL DECISION MODEL (17664057)

Main Inventor

Saurabh Trehan

Brief explanation

The patent application describes a method for predicting the condition of insulation on a cable that powers an electronic device. Here are the key points:

• The method determines the current insulation level of the cable based on a leakage test.
• It utilizes a supervised machine learning model to determine the current leakage and a confidence score for the insulation layer.
• A decision framework is generated based on the current leakage and confidence score to address any current leakage issues.
• The method performs actions based on the decision framework to fix the current leakage in the insulation layer.

Potential Applications

This technology can be applied in various industries and scenarios, including:

• Power distribution systems
• Electrical equipment maintenance
• Industrial automation
• Renewable energy systems

Problems Solved

This technology addresses the following problems:

• Identifying insulation issues in cables before they cause significant damage or failure.
• Enabling proactive maintenance and repair of insulation layers.
• Improving the reliability and safety of electronic devices and power systems.

Benefits

The use of this technology offers several benefits:

• Early detection of insulation problems, reducing the risk of electrical failures and accidents.
• Cost savings by preventing major damage or breakdowns.
• Increased efficiency in maintenance operations.
• Enhanced overall performance and lifespan of electronic devices and power systems.

Abstract

A method for a predictive insulation condition-based recommendation policy includes determining a present insulation level for an insulation layer on a cable providing power to an electronic device based on a current leakage test. The method also includes determining a current leakage and a confidence score for the insulation layer on the cable providing power to the electronic device utilizing a supervised machine learning model. The method also includes generating a decision framework for the electronic device based on the current leakage and the confidence score in response to determining to perform an action based on the decision framework for the electronic device, the method also includes performing the action based on the decision framework to address the current leakage for the insulation layer on the cable providing power to an electronic device.

DUAL-MULTIPLEXER FILTRATION OF INPUTTED QUBIT READOUT SIGNALS (17806862)

Main Inventor

Muir Kumph

Brief explanation

The patent application describes systems and techniques for filtering qubit readout signals using a dual-multiplexer circuit. Here is a simplified explanation of the abstract:

• The patent application introduces a device that can transmit signals to a qubit using a cable.
• The signals include both qubit readout signals and qubit control signals.
• The device includes a dual-multiplexer circuit located along the cable.
• The dual-multiplexer circuit can selectively attenuate the qubit readout signals.

Potential Applications

This technology has potential applications in various fields, including:

• Quantum computing: The dual-multiplexer filtration can improve the accuracy and reliability of qubit readout signals, enhancing the performance of quantum computing systems.
• Quantum communication: By filtering out unwanted noise and interference from qubit readout signals, this technology can enhance the quality and security of quantum communication systems.
• Quantum sensing: The dual-multiplexer circuit can help improve the sensitivity and precision of qubit-based sensors, enabling advancements in fields such as magnetic field detection and gravitational wave measurement.

Problems Solved

The technology addresses several problems in the field of quantum information processing, including:

• Signal interference: Qubit readout signals can be affected by noise and interference, leading to inaccurate measurements. The dual-multiplexer circuit filters out unwanted signals, reducing interference and improving the reliability of measurements.
• Signal attenuation: Some qubit readout signals may need to be attenuated to match the sensitivity range of measurement devices. The dual-multiplexer circuit allows for selective attenuation, ensuring optimal signal levels for accurate measurements.

Benefits

The use of dual-multiplexer filtration for qubit readout signals offers several benefits, including:

• Improved accuracy: By selectively attenuating unwanted signals, the technology improves the accuracy of qubit readout measurements, leading to more reliable results.
• Enhanced signal quality: Filtering out noise and interference improves the quality of qubit readout signals, enabling better analysis and interpretation of the data.
• Increased system performance: The technology optimizes the transmission of qubit readout signals, enhancing the overall performance of quantum computing, communication, and sensing systems.

Abstract

Systems and techniques that facilitate dual-multiplexer filtration of inputted qubit readout signals are provided. In various embodiments, a device can comprise a cable that can transmit an input signal to a qubit. In various aspects, the input signal can include at least one qubit readout signal and at least one qubit control signal. In various instances, the device can further comprise a dual-multiplexer circuit located along the cable. In various cases, the dual-multiplexer circuit can selectively attenuate the at least one qubit readout signal.

MULTIMODE COUPLER TO CONTROL INTERACTION BETWEEN QUANTUM BITS (17835511)

Main Inventor

Aaron Finck

Brief explanation

The patent application describes a device that includes two superconducting quantum bits (qubits) and a multimode coupler circuit. The coupler circuit has two modes and can operate in two states based on a control signal. 

• In the first state, the first qubit is connected to the first mode and the second qubit is connected to the second mode. This configuration prevents interaction between the two qubits.
• In the second state, both qubits are connected to both modes. This allows for an interaction between the qubits and enables an entanglement gate operation.

Potential applications of this technology:

• Quantum computing: The device can be used as a building block for quantum computers, where entanglement gates are crucial for performing complex calculations.
• Quantum communication: The entanglement gate operation can be utilized for secure quantum communication protocols, such as quantum key distribution.

Problems solved by this technology:

• Interaction suppression: The device provides a way to suppress interaction between qubits when not needed, which is important for maintaining the integrity of quantum information.
• Controlled interaction: The device allows for controlled interaction between qubits when desired, enabling entanglement gate operations.

Benefits of this technology:

• Scalability: The device can be easily integrated into larger quantum systems, allowing for the construction of more powerful quantum computers.
• Versatility: The ability to switch between different states of interaction provides flexibility in performing various quantum operations.
• Improved quantum communication: The entanglement gate operation enhances the capabilities of quantum communication protocols, leading to more secure and efficient communication.

Abstract

A device comprises first and second superconducting quantum bits, and a multimode coupler circuit coupled between the first and second superconducting quantum bits. The multimode coupler circuit comprises a first mode and a second mode, and is configured to operate in one of a first state and a second state, in response to a flux tuning control signal. In the first state, the first superconducting quantum bit is exchange coupled to the first mode, and the second superconducting quantum bit is exchange coupled to the second mode, to suppress interaction between the first and second superconducting quantum bits. In the second state, the first and second superconducting quantum bits are exchange coupled to both the first and second modes, to enable an interaction between the first and second superconducting quantum bits and perform an entanglement gate operation.

CONTROLLING INTERACTION BETWEEN COUPLED SUPERCONDUCTING QUANTUM BITS (17836268)

Main Inventor

Aaron Finck

Brief explanation

The patent application describes a device that includes two superconducting quantum bits (qubits) and a coupler circuit. The qubits consist of superconducting tunnel junctions and shunt inductors, forming separate loops. The coupler circuit is connected between the qubits and is designed to enable entanglement gate operations between them through exchange interactions. When driven by a control signal, the coupler circuit facilitates entanglement between the qubits, and when not driven, it suppresses interaction between them.

• The device includes two superconducting qubits and a coupler circuit.
• Each qubit consists of a superconducting tunnel junction and a shunt inductor, forming separate loops.
• The coupler circuit is connected between the qubits.
• The coupler circuit enables entanglement gate operations between the qubits through exchange interactions.
• The coupler circuit is driven by a control signal to facilitate entanglement between the qubits.
• When not driven by the control signal, the coupler circuit suppresses interaction between the qubits.

Potential Applications

• Quantum computing
• Quantum communication
• Quantum information processing

Problems Solved

• Facilitates entanglement gate operations between superconducting qubits.
• Suppresses unwanted interaction between qubits when not needed.

Benefits

• Enables efficient entanglement between qubits.
• Provides control over qubit interactions.
• Enhances the capabilities of quantum computing and communication systems.

Abstract

A device comprises a first superconducting quantum bit, a second superconducting quantum bit, and a coupler circuit. The first superconducting quantum bit comprises a superconducting tunnel junction and a shunt inductor which form a first superconducting loop. The second superconducting quantum bit comprises a superconducting tunnel junction and a shunt inductor which form a second superconducting loop. The coupler circuit is coupled between the first and second superconducting quantum bits. The coupler circuit is configured to implement an entanglement gate operation between the first and second superconducting quantum bits through exchange interactions between the coupler circuit and the first superconducting quantum bit and the second superconducting quantum bit, when the coupler circuit is driven by a control signal. The coupler circuit is configured to suppress interaction between the first superconducting quantum bit and the second superconducting quantum bit, when the coupler circuit is not driven by the control signal.

MULTIMODAL DATA INFERENCE (17806556)

Main Inventor

Andrea Giovannini

Brief explanation

The patent application describes a computer-implemented method for generating a machine learning model for multimodal data inference tasks. Here are the key points:

• The method involves encoding each sample in a training dataset of multimodal data samples to produce a compressed vector representation in a latent space.
• Features of the sample are perturbed to identify active features that significantly change the vector representation in each dimension of the latent space.
• A sample graph is generated with nodes representing features and edges indicating the active features for each dimension.
• A graph neural network model is trained using the sample graph to perform multimodal data inference tasks.
• This method can be used in multimodal data inference systems to improve the accuracy and efficiency of machine learning models.

Potential applications of this technology:

• Natural language processing: This method can be used to analyze and infer meaning from multimodal data sources such as text, images, and audio.
• Autonomous vehicles: The technology can help in processing and interpreting data from various sensors to make informed decisions.
• Healthcare: It can be applied to analyze medical data from different modalities to assist in diagnosis and treatment decisions.
• Fraud detection: The method can be used to analyze multiple data sources to identify patterns and anomalies indicative of fraudulent activities.

Problems solved by this technology:

• Efficient representation: The method provides a compressed vector representation of multimodal data samples, reducing the computational complexity of processing and analyzing large datasets.
• Feature selection: By identifying active features that significantly impact the vector representation, the method helps in selecting relevant features for inference tasks, improving accuracy and reducing noise.
• Multimodal integration: The sample graph and graph neural network model enable the integration of different modalities of data, allowing for more comprehensive and accurate inference.

Benefits of this technology:

• Improved accuracy: By considering multiple modalities of data and selecting relevant features, the method can enhance the accuracy of machine learning models for multimodal data inference tasks.
• Efficient processing: The compressed vector representation and feature selection help in reducing computational resources required for processing multimodal data.
• Flexibility: The method can be applied to various domains and tasks that involve multimodal data, providing a versatile solution for inference tasks.

Abstract

Computer-implemented methods are provided for generating machine learning model for multimodal data inference tasks. Such a method includes, for each sample in a training dataset of multimodal data samples, encoding the sample to produce a compressed vector representation of the sample in a k-dimensional latent space, and perturbing features of the sample to identify, for each dimension of the latent space, a set of active features perturbation of each of which produces more than a threshold change in the vector representation in that dimension. The method further comprises generating a sample graph having nodes interconnected by edges, wherein the nodes comprise nodes representing respective said features of the sample and edges interconnecting nodes indicate the active features for each dimension. The sample graph is then used to train a graph neural network model to perform the multimodal data inference task. Multimodal data inference systems employing such models are also provided.

INCREASING DATA DIVERSITY TO ENHANCE ARTIFICIAL INTELLIGENCE DECISIONS (17806307)

Main Inventor

Michael Boone

Brief explanation

The patent application describes a computer-based method, system, and program for improving artificial intelligence decisions by increasing data diversity. Here are the key points:

• The method involves generating a dataset of activities performed by workers at a facility.
• A specific activity is selected, and a plan is generated for completing that activity based on the dataset.
• Performance data is collected when the activity is completed using the generated plan.
• The dataset is updated with the collected performance data.
• The updated dataset is analyzed to identify areas where the efficiency of the plan can be improved.
• Based on the analysis, recommendations are made to modify the initial plan.

Potential applications of this technology:

• Enhancing decision-making processes in various industries such as manufacturing, logistics, and service sectors.
• Optimizing resource allocation and task assignment in complex operations.
• Improving efficiency and productivity in workforce management.

Problems solved by this technology:

• Lack of diverse and comprehensive data for training artificial intelligence systems.
• Inefficiencies in task planning and resource allocation.
• Difficulty in identifying areas for improvement in existing plans.

Benefits of this technology:

• Increased accuracy and effectiveness of artificial intelligence decisions.
• Enhanced efficiency and productivity in completing activities.
• Improved resource utilization and cost savings.
• Ability to adapt and optimize plans based on real-time performance data.

Abstract

Provided is a computer-implemented method, system, and computer program product for increasing data diversity to enhance artificial intelligence decisions. A processor may generate a corpus of data for a facility, the corpus of data having activities performed by workers at the facility. The processor may select an activity to be completed. The processor may generate, based on the corpus, a first plan for completing the activity, the first plan having a set of tasks for completing the activity and a set of workers to perform the tasks. The processor may collect performance data that is generated when completing the activity using the first plan. The processor may update the corpus of data with the performance data. The processor may analyze the updated corpus of data to identify an aspect for improving efficiency of the first plan. The processor may recommend, based on the analyzing, modification of the first plan.

SUPPORT DEVICE DEPLOYMENT (17806509)

Main Inventor

Akash U. Dhoot

Brief explanation

The abstract describes a method for providing a support device to assist personnel in performing tasks. The method involves receiving data values from various devices, including IoT and wearable devices, associated with the task being performed. These data values are compared to historical data values to identify the task being performed. If the received values exceed a predetermined threshold, it is determined whether the personnel require assistance. If assistance is needed, a support device is instructed to perform an action to assist the personnel.

• The method receives data values from IoT and wearable devices.
• The received data values are compared to historical data values.
• The method identifies the task being performed by the personnel.
• If the received values exceed a predetermined threshold, it is determined whether assistance is required.
• If assistance is needed, a support device is instructed to assist the personnel.

Potential Applications

• Industrial settings where personnel perform complex tasks that require monitoring and assistance.
• Healthcare environments where wearable devices and IoT devices can provide data on patient care tasks.
• Construction sites where safety and efficiency can be improved by monitoring and assisting personnel.

Problems Solved

• Lack of real-time monitoring and assistance for personnel performing tasks.
• Difficulty in identifying when personnel require assistance.
• Inefficient use of resources due to manual monitoring and assistance.

Benefits

• Improved safety and efficiency in task performance.
• Real-time monitoring and assistance for personnel.
• Optimal use of resources by providing assistance only when needed.

Abstract

A method providing a support device to assist personnel includes receiving data values from various devices associated with a task being performed by personnel, wherein the various devices include at least one Internet of Things (IoT) device and at least one wearable device. The method also includes comparing the received data values to historical data values associated with a pre-established knowledge corpus and identifying the task being performed by the personnel. In response to determining the received values exceed the historical values by a predetermined threshold for the task being performed by the personnel, the method includes determining whether the personnel require assistance with performing the task. In response to determining the personnel requires assistance with performing the task, the method includes instructing a support device to perform an action to assist the personnel with performing the task.

METHOD TO DETECT AND OBSTRUCT FRAUDULENT TRANSACTIONS (17835999)

Main Inventor

Doga Tav

Brief explanation

The abstract describes a computer-implemented method for detecting and obstructing skimmer devices in a network environment. Skimmer devices are unauthorized wireless devices that can intercept and steal sensitive information.

• The method involves monitoring wireless communications within the network environment.
• It identifies information associated with wireless communications transmitted by an unknown wireless device.
• Based on this information, it selects an obstruction rule.
• It then executes an obstruction action corresponding to the selected rule.

Potential Applications

This technology can be applied in various industries and settings where wireless communication security is crucial:

• Financial institutions: Preventing skimmer devices from stealing credit card information at ATMs or point-of-sale terminals.
• Retail stores: Protecting customer data from being compromised by skimmers placed on payment terminals.
• Government agencies: Safeguarding sensitive information transmitted over wireless networks.
• Healthcare facilities: Preventing unauthorized access to patient data transmitted wirelessly.
• Public Wi-Fi networks: Detecting and obstructing skimmers that may be intercepting user data.

Problems Solved

The technology addresses the following problems:

• Skimmer detection: It identifies unknown wireless devices that may be skimmer devices.
• Data theft prevention: By obstructing skimmer devices, it prevents the interception and theft of sensitive information.
• Network security: It enhances the security of wireless networks by detecting and obstructing unauthorized devices.

Benefits

The use of this technology offers several benefits:

• Enhanced security: It provides an additional layer of security to protect against skimmer devices.
• Real-time detection: It monitors wireless communications in real-time, allowing for immediate detection of potential threats.
• Customizable rules: The obstruction rules can be tailored to specific network environments, increasing effectiveness.
• Automated actions: The method automatically executes obstruction actions, minimizing the need for manual intervention.
• Cost-effective: By preventing data theft, it helps avoid financial losses and potential legal consequences.

Abstract

A computer-implemented method for detecting and obstructing skimmer devices is disclosed. The computer-implemented method includes monitoring wireless communications within a network environment. The computer-implemented method further includes identifying information associated with one or more wireless communications within the network environment transmitted by an unknown wireless device. The computer-implemented method further includes selecting an obstruction rule based, at least in part, on the information associated with the one or more wireless communications transmitted by the unknown wireless device. The computer-implemented method further includes executing an obstruction action corresponding to the selected obstruction rule.

LEASING DIGITAL ASSETS (17747141)

Main Inventor

Aaron K. Baughman

Brief explanation

The abstract describes a patent application that involves determining a price for using a digital asset from a repository and leasing it out for a specific time slot. The leased digital asset is integrated with the characteristics of a virtualized user and presented in a virtual environment during the time slot.

• The patent application focuses on determining the price for using a digital asset from a set of digital assets stored in a repository.
• It involves leasing out the digital asset for a specific time slot, allowing users to use it during that time in exchange for payment of the determined price.
• The leased digital asset is integrated with the base characteristics of a virtualized user, enhancing the user's experience in a virtual environment.
• The integrated leased digital asset is presented in a virtual environment during the specified time slot, providing users with access to the digital asset within the virtual environment.

Potential Applications

• This technology could be applied in the gaming industry, allowing users to lease and use digital assets within virtual games or simulations.
• It could also be utilized in virtual reality experiences, where users can lease and integrate digital assets into their virtual environments.
• The technology may find applications in digital art or design, enabling users to lease and incorporate digital assets into their creative projects.

Problems Solved

• The technology solves the problem of determining a fair price for using digital assets from a repository, ensuring that both the asset owner and the user are satisfied with the transaction.
• It addresses the challenge of integrating leased digital assets with the characteristics of a virtualized user, providing a seamless and immersive experience in virtual environments.
• The technology solves the issue of managing and presenting leased digital assets within a specified time slot, allowing users to access and utilize them during the designated period.

Benefits

• Users can access and use a variety of digital assets without the need for long-term ownership, reducing costs and providing flexibility.
• The integration of leased digital assets with the characteristics of a virtualized user enhances the user's experience and immersion in virtual environments.
• The technology enables asset owners to monetize their digital assets by leasing them out, creating new revenue streams.

Abstract

A price for use of a digital asset in a set of digital assets is determined. The set of digital assets stored in a digital asset repository. A time slot during which the digital asset is available for use is determined. The digital asset is leased out at the price and during the time slot, the leasing allowing use of the digital asset during the time slot in return for payment of the price. the leased digital asset is integrated with a set of base characteristics of a virtualized user. The integrated leased digital asset is presented in a virtual environment during the time slot.

ENHANCING GREENHOUSE GAS EMISSION ESTIMATES FOR STUBBLE BURNING AREAS (17805926)

Main Inventor

Jagabondhu Hazra

Brief explanation

The abstract describes a method, computer system, and computer program product for improving environmental impact estimations in agricultural areas. The invention involves obtaining data related to an agricultural area, deriving features from the data, identifying stubble burning areas based on these features, and determining the environmental impact of each identified stubble burning area.

• Obtaining data pertaining to an agricultural area
• Deriving one or more features from the agricultural data
• Identifying stubble burning areas within the agricultural areas based on the derived features
• Determining the environmental impact of each identified stubble burning area

Potential applications of this technology:

• Environmental monitoring and assessment in agricultural areas
• Identifying and addressing the impact of stubble burning on the environment
• Supporting decision-making processes for sustainable agricultural practices

Problems solved by this technology:

• Lack of accurate and efficient methods for estimating the environmental impact of stubble burning in agricultural areas
• Difficulty in identifying specific areas where stubble burning occurs
• Inadequate data for assessing the overall environmental impact of agricultural practices

Benefits of this technology:

• Improved accuracy and efficiency in estimating environmental impact
• Enhanced ability to identify and address the specific areas where stubble burning occurs
• Better understanding of the overall environmental impact of agricultural practices
• Support for sustainable and environmentally-friendly agricultural practices

Abstract

A method, computer system, and a computer program product for improving environmental impact estimations is provided. The present invention may include obtaining data pertaining to an agricultural area. The present invention may include deriving one or more features from the data pertaining to the agricultural area. The present invention may include identifying one or more stubble burning areas within the agricultural areas based on the one or more derived features. The present invention may include determining an environmental impact for each of the one or more stubble burning areas.

GAN ENABLED WELDING (17806356)

Main Inventor

Shailendra Moyal

Brief explanation

The abstract describes a method for performing a welding procedure using a virtual image of a structure. The method includes determining the conditions of the welding procedure, generating specifications based on the conditions, and creating a virtual reference shape by modifying the virtual image. The resulting shape of the welding procedure is compared to the virtual reference shape to determine the quality of the welding. Data pertaining to the welding procedure is also stored.

• Method for performing a welding procedure using a virtual image of a structure
• Determine conditions of the welding procedure
• Generate specifications for the welding procedure based on the conditions
• Create a virtual reference shape by modifying the virtual image
• Compare the resulting shape of the welding procedure with the virtual reference shape
• Determine the quality of the welding procedure based on the comparison
• Store data related to the welding procedure

Potential Applications

• Manufacturing industry
• Construction industry
• Automotive industry
• Aerospace industry

Problems Solved

• Ensures accurate and precise welding procedures
• Reduces the need for physical prototypes or trial-and-error methods
• Improves efficiency and productivity in welding processes

Benefits

• Saves time and resources by using virtual images and simulations
• Enhances the quality and reliability of welding procedures
• Allows for better planning and optimization of welding processes
• Provides a digital record of welding data for future reference and analysis

Abstract

A method for performing a welding procedure includes determining conditions of the welding procedure using a virtual image of a structure on which the welding procedure is to be performed. The method further includes generating specifications for performing the welding procedure based on the conditions. The method further includes generating a virtual reference shape based on the conditions and the specifications, the virtual reference shape generated by modifying the virtual image. The method further includes comparing a resulting shape of the welding procedure with the virtual reference shape. The method further includes determining a quality of the welding procedure based on the comparison. The method further includes storing data pertaining to the welding procedure.

SCENARIO AWARE DYNAMIC CODE BRANCHING OF SELF-EVOLVING CODE (17806794)

Main Inventor

Saraswathi Sailaja Perumalla

Brief explanation

The patent application describes computer technology that allows an AI-enabled edge device, such as an autonomous vehicle or industrial robotic device, to dynamically adapt its code based on successful execution of a contextual scenario. This technology predicts a second contextual scenario where the device can perform a specific activity and proactively deploys self-adapted code on the device.

• The technology enables dynamic code branching of self-adapted code on an AI-enabled edge device.
• It relies on the successful execution of a contextual scenario by the device.
• The technology predicts a second contextual scenario where the device can perform a predetermined activity.
• It proactively deploys self-adapted code on the device to handle the predicted scenario.

Potential Applications

This technology has potential applications in various fields, including:

• Autonomous vehicles: The AI-enabled edge device can adapt its code based on successful execution of contextual scenarios, improving its ability to handle different driving situations.
• Industrial robotics: The technology allows robotic devices to dynamically adapt their code to perform specific activities based on contextual scenarios, enhancing their efficiency and versatility.
• Smart home systems: AI-enabled edge devices in smart homes can use this technology to adapt their code and perform different tasks based on changing environmental conditions or user preferences.

Problems Solved

The technology addresses several problems:

• Lack of adaptability: Traditional code in AI-enabled edge devices is typically static and cannot adapt to changing scenarios. This technology solves this problem by enabling dynamic code branching and self-adaptation.
• Inefficiency: Without proactive deployment of self-adapted code, AI-enabled edge devices may not be able to efficiently handle predicted scenarios. This technology solves this problem by proactively deploying the necessary code.
• Limited versatility: AI-enabled edge devices may have limited capabilities to handle different contextual scenarios. This technology solves this problem by predicting and preparing for specific scenarios, expanding the device's range of applications.

Benefits

The technology offers several benefits:

• Improved performance: By dynamically adapting its code, the AI-enabled edge device can optimize its performance based on successful execution of contextual scenarios.
• Enhanced efficiency: Proactively deploying self-adapted code allows the device to efficiently handle predicted scenarios, reducing response times and resource consumption.
• Increased versatility: The ability to predict and prepare for specific scenarios enables the device to perform a wider range of activities, making it more versatile and adaptable to different environments.

Abstract

Computer technology for performing dynamic code branching of self-adapted code upon successful execution of a contextual scenario by artificial intelligence (AI) enabled edge device (for example, an autonomous vehicle or an industrial robotic device). predicting a second contextual scenario where the AI enabled edge device can perform a predetermined activity, and proactively deploying self-adapted code on the AI enabled edge device.

ENHANCING VIDEO LANGUAGE LEARNING BY PROVIDING CATERED CONTEXT SENSITIVE EXPRESSIONS (18450848)

Main Inventor

I-Hsiang Liao

Brief explanation

The patent application describes a computer processing system that enhances video-based language learning. Here are the key points:

• The system includes a video server that stores videos in different languages for learning purposes.
• A video metadata database is used to store translations of sentences spoken in the videos, character profiles, and mappings between sentences and learner profiles.
• A learner profile database stores information about the learners.
• A semantic analyzer and matching engine analyze the translations of sentences in a video and find alternative sentences that align with the learner's profile.
• A presentation system plays the video and provides the learner with the alternative sentences.

Potential applications of this technology:

• Language learning platforms or apps could use this system to provide personalized language learning experiences.
• Educational institutions could incorporate this system into their language courses to enhance the learning process.

Problems solved by this technology:

• Language learners often struggle to find appropriate learning materials that match their proficiency level and interests. This system solves this problem by providing personalized video content and alternative sentences.
• Learners may get discouraged if they encounter sentences in videos that are too difficult for them. The system addresses this issue by offering alternative sentences that are more suitable for the learner's level.

Benefits of this technology:

• Personalized learning: Learners can receive tailored language learning content based on their profile and preferences.
• Enhanced engagement: By providing alternative sentences, learners can better understand and practice the language, leading to increased engagement and motivation.
• Efficient learning: The system helps learners overcome language barriers by offering alternative sentences, allowing them to progress at their own pace.

Abstract

A computer processing system is provided for enhancing video-based language learning. The system includes a video server for storing videos that use one or more languages to be learned. The system further includes a video metadata database for storing translations of sentences uttered in the videos, character profiles of characters appearing in the videos, and mappings between the sentences and a learner profile. The system also includes a learner profile database for storing learner profiles. The system additionally includes a semantic analyzer and matching engine for finding, for at least a given video and a given learner, alternative sentences for and responsive to the translations of the sentences uttered in the given video that conflict with a respective learner profile for the given learner. The computer processing system further includes a presentation system for playing back the given video and providing the alternative sentences to the given learner.

GENERATING MULTI-TURN DIALOG DATASETS (17805946)

Main Inventor

Zilu Tang

Brief explanation

The embodiment described in this patent application is a method for generating multi-turn dialog datasets to train dialog or conversational agents. Here are the key points:

• The embodiment selects an agent from a set of agents.
• It automatically identifies sentences from the training data of the selected agent that meet a specific condition in a random dialog node.
• It determines an approach to respond to the condition in the dialog node, either by satisfying the condition or inserting a multi-turn conversational property.
• It generates a response based on the determined approach.
• It repeats the process for subsequent sequential child nodes, determining approaches to respond to each condition and generating corresponding responses.
• It collects and stores data related to the selected agent and the generated responses.

Potential applications of this technology:

• Training dialog or conversational agents: This method can be used to generate datasets for training AI agents to engage in multi-turn conversations.
• Virtual assistants: The generated datasets can be used to improve the conversational abilities of virtual assistants, making them more effective in understanding and responding to user queries.
• Customer service chatbots: By training chatbots with multi-turn dialog datasets, they can provide more natural and context-aware responses to customer inquiries.

Problems solved by this technology:

• Lack of multi-turn dialog datasets: Generating high-quality datasets for training dialog agents can be time-consuming and resource-intensive. This method automates the process, making it more efficient.
• Contextual understanding: By considering the sequential nature of dialog nodes and generating responses that maintain context, this method helps dialog agents better understand and respond to user queries.

Benefits of this technology:

• Improved training data quality: The method ensures that the generated datasets satisfy specific conditions and include multi-turn conversational properties, leading to more effective training of dialog agents.
• Time and resource efficiency: Automating the dataset generation process saves time and resources compared to manual creation.
• Enhanced conversational abilities: Dialog agents trained with datasets generated using this method can provide more context-aware and natural responses, improving user experience.

Abstract

An embodiment for generating multi-turn dialog datasets for training of dialog or conversational agents. The embodiment may select an agent from a set of agents. The embodiment may automatically identify sentences from training data of the selected agent that satisfy a first sequential node condition of the selected random dialog node. The embodiment may automatically determine an approach for responding to the first sequential node condition of the selected random dialog node that either satisfies the first sequential dialog node condition, or inserts a multi-turn conversational property, and generate a corresponding response. The embodiment may automatically determine additional approaches for responding to each condition within subsequent sequential child nodes of the selected random dialog node that either satisfy each subsequent sequential child node condition or insert a multi-turn conversational property, and generate corresponding responses. The embodiment may collect and store data relating to the selected agent and the generated responses.

INDIVIDUAL RECOGNITION USING VOICE DETECTION (17806286)

Main Inventor

ETHAN S. HEADINGS

Brief explanation

The patent application describes a method, computer program, and system for determining the name of an individual based on voice detection. Here is a simplified explanation of the abstract:

• The method involves analyzing the voice characteristics of an individual based on an audio input received through an audio input device.
• The voice characteristics are compared to voice profiles to find a match.
• If the voice characteristics of the individual and a voice profile meet a similarity threshold, the method determines the name associated with that voice profile.
• The determined name is then provided to a user who is having a conversation with the individual.

Potential applications of this technology:

• Voice-based identification systems: This technology can be used in voice recognition systems to identify individuals based on their voice characteristics.
• Personalized customer service: Companies can use this technology to personalize customer interactions by identifying customers based on their voice and providing relevant information.
• Security systems: Voice-based identification can be used in security systems to grant access to authorized individuals.

Problems solved by this technology:

• Identification accuracy: This technology improves the accuracy of identifying individuals based on their voice characteristics, reducing the chances of misidentification.
• Efficiency: By automating the process of determining an individual's name based on their voice, this technology saves time and effort compared to manual identification methods.

Benefits of this technology:

• Enhanced user experience: Users can be addressed by their names, providing a personalized and more engaging experience.
• Improved security: Voice-based identification adds an extra layer of security, as voice characteristics are unique to individuals.
• Time-saving: Automated identification based on voice characteristics eliminates the need for manual identification processes, saving time for both users and businesses.

Abstract

A method, a computer program product, and a computer system determine a name of an individual based on voice detection. The method includes determining voice characteristics of a voice of the individual based on an audio input received and recorded via an audio input device. The method includes comparing the voice characteristics of the voice to further voice characteristics of voice profiles. The method includes as a result of the voice and one of the voice profiles meeting a similarity threshold, determining a name associated with the one of the voice profile. The method includes providing the name to a user who is having a conversation with the individual.

SIMULTANEOUS ELECTRODES FOR MAGNETO-RESISTIVE RANDOM ACCESS MEMORY DEVICES (17806594)

Main Inventor

Oscar van der Straten

Brief explanation

The patent application describes a memory device that includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. The device utilizes various layers and materials to improve its performance and functionality.

• The memory device includes a magnetic tunnel junction (MTJ) pillar, which is a key component for storing and retrieving data.
• An amorphous dielectric hardmask is in contact with a portion of the uppermost surface of the MTJ pillar. This hardmask helps protect and stabilize the MTJ pillar.
• A metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with another portion of the uppermost surface of the MTJ pillar. This metal layer serves as the top electrode of the memory device.
• A dielectric underlayer is in contact with a portion of the bottommost surface of the MTJ pillar. This underlayer provides insulation and support for the MTJ pillar.
• Another portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer and in contact with another portion of the bottommost surface of the MTJ pillar. This metal layer acts as the bottom electrode of the memory device.

Potential applications of this technology:

• Memory devices: The described structure and materials can be used in various memory devices, such as non-volatile memory or random-access memory.
• Data storage: The improved memory device can be used for storing and retrieving data in electronic devices, such as computers, smartphones, or IoT devices.

Problems solved by this technology:

• Stability and protection: The amorphous dielectric hardmask helps stabilize the MTJ pillar and protect it from external factors, improving the reliability and longevity of the memory device.
• Insulation and support: The dielectric underlayer provides insulation and support for the MTJ pillar, reducing the risk of interference and enhancing the performance of the memory device.

Benefits of this technology:

• Improved performance: The described structure and materials enhance the performance of the memory device, allowing for faster and more efficient data storage and retrieval.
• Enhanced reliability: The stability and protection provided by the amorphous dielectric hardmask increase the reliability and lifespan of the memory device.
• Reduced interference: The dielectric underlayer helps reduce interference and improve the overall functionality of the memory device.

Abstract

A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. An amorphous dielectric hardmask is in contact with a first portion of an uppermost surface of the MTJ pillar. A first portion of a metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with a second portion of the uppermost surface of the MTJ pillar extending outwards from the amorphous dielectric hardmask for providing the top electrode. A dielectric underlayer is in contact with a first portion of a bottommost surface of the MTJ pillar, while a second portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer. The second portion of the metal layer is in contact with a second portion of the bottommost surface of the MTJ pillar extending outwards from the dielectric underlayer for providing the bottom electrode.

COAXIAL TOP MRAM ELECTRODE (17806790)

Main Inventor

Oscar van der Straten

Brief explanation

The abstract describes a semiconductor structure that includes a magneto-resistive random access memory (MRAM) pillar and a coaxial top electrode. The MRAM pillar consists of several layers, including a bottom electrode layer, a reference layer, a free layer, and a tunnel barrier. The top electrode has a smaller diameter than the MRAM pillar.

• The semiconductor structure includes a magneto-resistive random access memory (MRAM) pillar.
• The MRAM pillar has a bottom electrode layer, a reference layer, a free layer, and a tunnel barrier.
• The MRAM pillar has a specific diameter.
• The semiconductor structure also includes a coaxial top electrode.
• The top electrode has a smaller diameter than the MRAM pillar.

Potential applications of this technology:

• Memory devices: The semiconductor structure can be used in memory devices, such as MRAM, which offer non-volatile storage capabilities.
• Computing systems: The technology can be integrated into computing systems to provide fast and reliable memory access.
• Data storage: The semiconductor structure can be used in data storage devices, enabling high-density and low-power storage solutions.

Problems solved by this technology:

• Non-volatile memory: The MRAM pillar provides non-volatile memory storage, meaning data is retained even when power is lost.
• Scalability: The coaxial top electrode with a smaller diameter allows for better scalability and integration of the semiconductor structure into smaller devices.
• Reliability: The structure's design ensures reliable and stable memory operations, reducing the risk of data loss or corruption.

Benefits of this technology:

• Fast access times: The MRAM pillar offers fast read and write speeds, enabling quick data retrieval and storage.
• Low power consumption: MRAM technology is known for its low power requirements, resulting in energy-efficient devices.
• High endurance: The semiconductor structure has high endurance, allowing for a large number of read and write cycles without degradation.
• Compact design: The smaller diameter of the top electrode enables the integration of the semiconductor structure into smaller and more compact devices.

Abstract

Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter.

VIA CONNECTION TO BACKSIDE POWER DELIVERY NETWORK (17806280)

Main Inventor

Ruilong Xie

Brief explanation

The abstract of the patent application describes a semiconductor structure that includes a middle-of-line contact, a backside power rail, and a contact via connecting them. The contact via has two portions - a first portion with a negative tapered profile and a second portion with a positive tapered profile.

• The semiconductor structure includes a middle-of-line contact, a backside power rail, and a contact via.
• The contact via connects the middle-of-line contact and the backside power rail.
• The contact via has a first portion with a negative tapered profile.
• The contact via also has a second portion with a positive tapered profile.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit design and fabrication

Problems solved by this technology:

• Efficient and reliable connection between middle-of-line contacts and backside power rails in a semiconductor structure
• Improved electrical performance and signal transmission

Benefits of this technology:

• Enhanced performance and reliability of semiconductor devices
• Improved power distribution and signal integrity
• Increased efficiency in semiconductor manufacturing processes

Abstract

A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

HIGH ASPECT RATIO BURIED POWER RAIL METALLIZATION (17806570)

Main Inventor

Sagarika Mukesh

Brief explanation

The patent application describes a semiconductor component that includes a trench formed in a substrate, with a dielectric material extending below the substrate's surface. The trench is coated with a non-metal liner, which is then coated with a metal liner. A power rail is formed in the trench, in direct contact with either the metal liner or the non-metal liner, extending into the dielectric material and above the substrate's surface.

• A semiconductor component with a trench formed in a substrate
• Dielectric material extending below the substrate's surface
• Non-metal liner coating the interior surfaces of the trench
• Metal liner coating the interior surfaces of the non-metal liner
• Power rail formed in the trench, in contact with the metal or non-metal liner
• Power rail extends into the dielectric material and above the substrate's surface

Potential Applications

• Power electronics
• Integrated circuits
• Semiconductor devices

Problems Solved

• Improved power distribution in semiconductor components
• Enhanced electrical performance
• Increased power handling capabilities

Benefits

• Efficient power distribution
• Enhanced electrical conductivity
• Improved power handling capacity

Abstract

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS (17806602)

Main Inventor

Tao Li

Brief explanation

The abstract describes a semiconductor device that includes two stacked transistors and power rails on both the frontside and backside. It also includes multiple signal lines, one of which is connected to the source/drain epitaxy of the second transistor through a backside contact and an interlevel via.

• The semiconductor device consists of two stacked transistors.
• It has a frontside power rail connected to the first transistor's source/drain epitaxy.
• It has a backside power rail connected to the second transistor's source/drain epitaxy.
• The device includes multiple frontside signal lines.
• One of the frontside signal lines is connected to the second transistor's source/drain epitaxy through a backside contact and an interlevel via.

Potential Applications

• This semiconductor device can be used in various electronic devices and systems that require high-performance transistors.
• It can be utilized in applications such as integrated circuits, microprocessors, memory devices, and power management systems.

Problems Solved

• The stacked transistor design allows for increased circuit density and improved performance.
• The use of frontside and backside power rails enables efficient power distribution.
• The connection of signal lines through backside contacts and interlevel vias allows for better signal transmission and integration.

Benefits

• The stacked transistor configuration provides higher integration density, allowing for more functionality in a smaller footprint.
• The frontside and backside power rails ensure efficient power delivery, reducing power losses and improving overall performance.
• The connection of signal lines through backside contacts and interlevel vias enhances signal integrity and reduces signal interference.

Abstract

Provided is a semiconductor device. The semiconductor device comprises a first transistor stacked above a second transistor. The semiconductor device further includes a frontside power rail that is electrically coupled to a source/drain epitaxy of the first transistor. The semiconductor device further includes a backside power rail that is electrically coupled to a source/drain epitaxy of the second transistor. The semiconductor device further includes a plurality of frontside signal lines. The plurality of signal lines includes a first frontside signal line that is electrically coupled to a source/drain epitaxy of the second transistor. The frontside signal line is connected to the source/drain epitaxy through a backside contact and an interlevel via.

SKIP-LEVEL TSV WITH HYBRID DIELECTRIC SCHEME FOR BACKSIDE POWER DELIVERY (17837434)

Main Inventor

Nicholas Anthony Lanzillo

Brief explanation

The abstract describes a skip-level through-silicon via structure that allows for low resistance via connection for backside power distribution. This structure skips one or more intermediate backside metal layers, providing greater design flexibility for power grid. It has a larger size compared to conventional through-silicon via structures, resulting in lower through-silicon via resistance.

• Skip-level through-silicon via structure enables low resistance via connection for backside power distribution.
• It skips one or more intermediate backside metal layers, providing greater design flexibility for power grid.
• The structure has a larger size, resulting in lower through-silicon via resistance compared to conventional structures.

Potential Applications

This technology can be applied in various fields where efficient power distribution is required, such as:

• Integrated circuits
• Microprocessors
• Power electronics
• Data centers

Problems Solved

The skip-level through-silicon via structure addresses the following problems:

• High resistance in via connections for backside power distribution
• Limited design flexibility for power grid
• Inefficient power distribution in integrated circuits and microprocessors

Benefits

The benefits of the skip-level through-silicon via structure include:

• Low resistance via connection for efficient power distribution
• Greater design flexibility for power grid
• Improved power distribution in integrated circuits and microprocessors
• Enhanced performance and reliability of power electronics and data centers

Abstract

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

SQUARE-SHAPED CONTACT WITH IMPROVED ELECTRICAL CONDUCTIVITY (17806514)

Main Inventor

Kangguo Cheng

Brief explanation

The patent application describes a semiconductor structure with rectangular or square-shaped contact vias in a semiconductor material. These contact vias have straight edges parallel to the crystal planes of the material and corners pointing in a direction orthogonal to the crystal planes.

• The semiconductor structure includes rectangular or square-shaped contact vias in a semiconductor material.
• The contact vias have straight edges parallel to the crystal planes of the material.
• The corners of the contact vias point in a direction orthogonal to the crystal planes.
• This design provides a larger contact area compared to conventional round-shaped contact vias with the same width.

Potential Applications

• Semiconductor devices
• Integrated circuits
• Microprocessors
• Power electronics

Problems Solved

• Limited contact area in conventional round-shaped contact vias
• Improved electrical performance and reliability

Benefits

• Larger contact area for improved electrical performance
• Enhanced reliability of semiconductor devices
• Potential for higher power handling capabilities

Abstract

An approach provides a semiconductor structure with one or more rectangular or square-shaped contact vias in a semiconductor material. The semiconductor device includes one of the first element of the semiconductor device element under the square-shaped contact via or the second element of the semiconductor device element above the square-shaped contact via. The semiconductor structure includes the square-shaped via in the semiconductor material that has straight edges that are parallel to one or more of the (110) crystal planes of the semiconductor material and the square-shaped contact vias has corners pointing in a direction orthogonal to one or more of the (100) crystal planes of the semiconductor material. The square-shaped contact via provides a larger contact area that a conventional round-shaped contact via with a diameter matching the width of the square-shaped contact via.

STACKED FIELD EFFECT TRANSISTOR (17806292)

Main Inventor

Brent A. Anderson

Brief explanation

The abstract describes a semiconductor device that includes a bottom field effect transistor (FET) with a bottom source-drain epitaxial layer, a top FET stacked over the bottom FET, a back-end-of-line (BEOL) layer, a bottom gate contact that extends laterally over the bottom source-drain epitaxial layer, and a top gate contact that connects the bottom gate contact to the BEOL layer.

• The semiconductor device includes a bottom FET and a top FET stacked on top of each other.
• The bottom FET has a bottom source-drain epitaxial layer formed on its sides.
• A back-end-of-line (BEOL) layer is formed on top of the top FET.
• The bottom gate contact is in contact with the bottom FET and has an extending portion that extends laterally over the bottom source-drain epitaxial layer.
• The top gate contact is in contact with the extending portion of the bottom gate contact and electrically connects it to the BEOL layer.

Potential Applications

• This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
• It can be applied in power management circuits, memory devices, and microprocessors.

Problems Solved

• The device solves the problem of integrating a bottom FET and a top FET in a compact and efficient manner.
• It addresses the challenge of connecting the bottom gate contact to the BEOL layer.

Benefits

• The device allows for improved performance and functionality of electronic devices.
• It enables better power management and faster processing speeds.
• The compact design of the device saves space and allows for more efficient circuit integration.

Abstract

A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

STAIRCASE STACKED FIELD EFFECT TRANSISTOR (17806340)

Main Inventor

Sanjay C. Mehta

Brief explanation

The abstract describes a semiconductor device that includes a bottom field effect transistor (FET) and a smaller top FET stacked over it. The device also includes a bottom gate, a top gate, and a bottom contact adjacent to the top gate, with an inner spacer between them.

• The semiconductor device includes a stacked configuration of a bottom FET and a smaller top FET.
• The bottom FET and top FET have different active areas.
• The device includes a bottom gate in contact with the bottom FET and a top gate in contact with the top FET.
• A bottom contact is formed adjacent to the top gate.
• An inner spacer is formed between the bottom contact and the top gate.

Potential Applications

• This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
• It can be utilized in power management circuits, amplifiers, and memory devices.

Problems Solved

• The stacked configuration of the bottom and top FETs allows for improved performance and functionality of the semiconductor device.
• The use of the inner spacer helps to optimize the electrical characteristics and reduce interference between the bottom contact and top gate.

Benefits

• The smaller active area of the top FET allows for better control and efficiency in the semiconductor device.
• The stacked configuration and use of the inner spacer enhance the overall performance and reliability of the device.
• The semiconductor device can provide improved power management, amplification, and memory capabilities.

Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a bottom field effect transistor (FET); a top FET stacked over the bottom FET, where the top FET has a smaller active area than the bottom FET; a bottom gate formed in contact with the bottom FET; a top gate formed in contact with the top FET; and a bottom contact formed adjacent to the top gate, wherein an inner spacer is formed between the bottom contact and the top gate.

MOON-SHAPED BOTTOM SPACER FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR (VTFET) DEVICES (18232640)

Main Inventor

Ruilong Xie

Brief explanation

The abstract describes a patent application for a uniform moon-shaped bottom spacer for a VTFET (Vertical Tunneling Field Effect Transistor) device. The innovation involves replacing the bottom spacer of the device with a moon-shaped spacer that is epitaxially grown above a bottom source/drain region.

• The replacement bottom spacer is accessed, removed, and then replaced with a moon-shaped spacer.
• The moon-shaped spacer is grown epitaxially above the bottom source/drain region.
• A trench is formed in the substrate and filled with a dielectric fill material that covers the replacement bottom spacer.
• The uniform moon-shaped bottom spacer improves the performance and efficiency of the VTFET device.

Potential Applications

• Semiconductor industry
• Electronics manufacturing
• Integrated circuit design

Problems Solved

• Inefficient performance of VTFET devices
• Lack of uniformity in bottom spacers
• Difficulties in accessing and replacing bottom spacers

Benefits

• Improved performance and efficiency of VTFET devices
• Uniformity in the shape and structure of bottom spacers
• Simplified process for accessing and replacing bottom spacers

Abstract

A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

UNIFORM SEMICONDUCTOR ACTIVE FIN WIDTH (17837150)

Main Inventor

Min Gyu Sung

Brief explanation

The abstract describes a semiconductor device and its formation. The device consists of a group of fins arranged in an array. The upper portion of each fin above a shallow trench isolation layer has a similar profile. However, the bottom portion of the inner fins below the isolation layer has a different profile compared to the bottom portion of the edge fins. The width of the bottom portion of the edge fins is greater than the width of the bottom portion of the inner fins.

• The semiconductor device includes a fin array with fins grouped together.
• The upper portion of each fin above the isolation layer has a similar profile.
• The bottom portion of the inner fins below the isolation layer has a different profile compared to the edge fins.
• The width of the bottom portion of the edge fins is greater than the width of the bottom portion of the inner fins.

Potential Applications

• This technology can be used in the manufacturing of semiconductor devices.
• It may find applications in various electronic devices such as computers, smartphones, and IoT devices.

Problems Solved

• The different profiles of the bottom portions of the inner and edge fins help optimize the performance and functionality of the semiconductor device.
• The wider bottom portion of the edge fins allows for better heat dissipation and electrical conductivity.

Benefits

• The similar profile of the upper portions of the fins ensures uniformity and consistency in the device.
• The different profiles of the bottom portions of the fins provide specific advantages for different areas of the device.
• The wider bottom portion of the edge fins improves heat dissipation and electrical conductivity, leading to better overall performance.

Abstract

A semiconductor device and formation thereof. The semiconductor device includes a plurality of fins grouped in a fin array. A first profile of an upper portion of each of the plurality of fins in the fin array located above a top surface of a shallow trench isolation layer is substantially similar. A second profile of a bottom portion of one or more inner fins in the fin array located below the shallow trench isolation layer is different than a third profile of the bottom portion of edge fins in the fin array located below the shallow trench isolation layer. A width of the bottom portion of the edge fins in the fin array located below the shallow trench isolation layer is greater than a width of the bottom portion of the one or more inner fins in the fin array located below the shallow trench isolation layer.

SEGMENTED DIGITAL-TO-ANALOG CONVERTER WIRELINE DRIVER (17839141)

Main Inventor

Martin Cochet

Brief explanation

The abstract describes an apparatus that consists of A-type and B-type resistance segments, each comprising switches, linear resistors, tunable header units, and tunable footer units. The second terminals of the A-type and B-type linear resistors are connected together.

• The apparatus includes A-type and B-type resistance segments with various components.
• A-type resistance segments have A-type switches, A-type linear resistors, A-type tunable header units, and A-type tunable footer units.
• B-type resistance segments have B-type switches, B-type linear resistors, B-type tunable header units, and B-type tunable footer units.
• The second terminals of the A-type and B-type linear resistors are interconnected.

Potential applications of this technology:

• Electrical circuit design and implementation.
• Signal processing and filtering.
• Variable resistance control in electronic systems.
• Tunable impedance matching in communication systems.

Problems solved by this technology:

• Provides a flexible and tunable resistance configuration.
• Enables precise control over resistance values.
• Facilitates impedance matching in electronic systems.
• Allows for efficient signal processing and filtering.

Benefits of this technology:

• Improved versatility and adaptability in circuit design.
• Enhanced control and precision in resistance settings.
• Increased efficiency and performance in electronic systems.
• Simplified impedance matching and signal processing.

Abstract

An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

MACHINE LEARNING NETWORK EXTENSION BASED ON HOMOMORPHIC ENCRYPTION PACKINGS (17838901)

Main Inventor

Nir DRUCKER

Brief explanation

The abstract of the patent application describes a system that utilizes machine learning networks and homomorphic encryption (HE) packing frameworks. The system includes a processor that can generate a list of HE packings for the machine learning network based on the selected HE packing framework. The processor can then extend the machine learning network by adding additional neurons based on the generated list of HE packings. The extended machine learning network can also be trained by the processor.

• The system includes a processor that receives a machine learning network and a selected homomorphic encryption (HE) packing framework.
• The processor generates a list of HE packings for the machine learning network based on the selected HE packing framework.
• The machine learning network is extended by the processor by adding additional neurons based on the generated list of HE packings.
• The extended machine learning network can be trained by the processor.

Potential Applications

This technology has potential applications in various fields, including:

• Secure machine learning: The use of homomorphic encryption allows for the secure processing of sensitive data in machine learning applications.
• Privacy-preserving analytics: By encrypting the data and performing computations on encrypted data, privacy can be maintained while still gaining insights from the data.
• Secure data sharing: Homomorphic encryption enables secure sharing of data between different parties without revealing the actual data.

Problems Solved

This technology solves several problems in the field of machine learning and data security, including:

• Data privacy: Homomorphic encryption ensures that sensitive data remains encrypted throughout the processing, preventing unauthorized access to the data.
• Secure computation: The use of homomorphic encryption allows for secure computations on encrypted data, ensuring that the results are also encrypted and protected.
• Secure data sharing: The ability to perform computations on encrypted data enables secure sharing of data between different parties without exposing the actual data.

Benefits

The use of this technology offers several benefits, including:

• Enhanced data privacy: By utilizing homomorphic encryption, sensitive data can be protected throughout the entire machine learning process.
• Secure machine learning: The combination of machine learning networks and homomorphic encryption provides a secure environment for processing and analyzing sensitive data.
• Collaborative data analysis: Homomorphic encryption enables secure collaboration and sharing of data between different parties, fostering collaboration and innovation in data-driven fields.

Abstract

An example system includes a processor to receive a machine learning network and a selected homomorphic encryption (HE) packing framework. The processor can generate list of HE packings for the machine learning network based on the selected HE packing framework. The processor can extend the machine learning network to include additional neurons based on the list of HE packings. The processor can also train the extended machine learning network.

SMART ROUND ROBIN DELIVERY FOR HARDWARE SECURITY MODULE HOST REQUESTS (17806515)

Main Inventor

Surya V. Duggirala

Brief explanation

The abstract describes a method, computer program product, and system for handling host requests on a hardware security module (HSM). Here is a simplified explanation of the abstract:

• The method involves selecting a domain (group) with the longest wait time for a host request on the HSM.
• The oldest host request requested by the selected domain is then chosen.
• The method determines the type of hardware engine required to process the oldest host request.
• It also determines if the saturation level of the hardware engine type exceeds a saturation threshold.
• If the saturation level exceeds the threshold, a second host request from the selected domain that uses a different hardware engine type is selected.
• The second host request is processed using the different hardware engine type of the HSM.
• Unprocessed host requests from the domains are continuously selected to ensure efficient processing on the HSM.

Potential Applications:

• This technology can be applied in any system that utilizes a hardware security module (HSM) to handle host requests.
• It can be used in industries that require secure processing of sensitive data, such as banking, healthcare, and government sectors.

Problems Solved:

• The technology addresses the issue of efficiently handling host requests on a hardware security module (HSM) by selecting the most appropriate requests based on wait time and hardware engine type.
• It helps prevent bottlenecks and delays in processing host requests, ensuring optimal performance of the HSM.

Benefits:

• The method ensures efficient utilization of the hardware resources of the HSM by selecting the most suitable host requests based on wait time and hardware engine type.
• It improves the overall performance and responsiveness of the system by preventing saturation of hardware engine types.
• The continuous selection of unprocessed host requests ensures a smooth and streamlined processing flow on the HSM.

Abstract

A method, a computer program product, and a system are provided that handles host requests on a hardware security module (HSM). The method includes selecting a domain with a longest wait time with a host request for the HSM and selecting an oldest host request requested by the domain. The method also includes determining a hardware engine type required to process the oldest host request and determining a saturation level of the hardware engine type exceeds a saturation threshold. The method further includes selecting a second host request requested by the domain that uses a different hardware engine type based on the saturation level exceeding the saturation threshold and processing the second host request using the different hardware engine type of the HSM. The method further includes selecting unprocessed host requests of the domains to continuously provide efficient selection of those host requests to the HSM.

AGGREGATE ANONYMOUS CREDENTIALS FOR DECENTRALIZED IDENTITY IN BLOCKCHAIN (17805894)

Main Inventor

Kaoutar El Khiyaoui

Brief explanation

The patent application describes a system that verifies user attributes using cyclic groups, anonymous credentials, and multi-signatures. Here are the key points:

• The system generates cyclic groups to establish a secure framework for attribute verification.
• It generates an aggregate anonymous credential by combining credentials from regulatory authorities and issuers.
• An issuer is set up with a multi-signature, ensuring that administrators collectively validate user credentials.
• User credentials are generated to authenticate and authorize user operations.
• The system validates operations signed with user credentials, ensuring their authenticity and integrity.

Potential Applications

This technology has potential applications in various fields, including:

• Identity verification systems: The system can be used to securely verify user attributes and credentials, enhancing identity verification processes.
• Access control systems: By validating user credentials, the system can be applied to control access to sensitive information or restricted areas.
• Financial services: The technology can be utilized to enhance the security and privacy of financial transactions, protecting user credentials and preventing fraud.

Problems Solved

The system addresses several problems related to attribute verification and credential management, including:

• Security risks: By using cyclic groups and multi-signatures, the system mitigates security risks associated with unauthorized access and credential tampering.
• Privacy concerns: The use of anonymous credentials protects user privacy by not revealing specific personal information during attribute verification.
• Trustworthiness of credentials: The system ensures the trustworthiness of user credentials by validating them through a multi-signature process, reducing the risk of fraudulent or forged credentials.

Benefits

The technology offers several benefits, including:

• Enhanced security: The system's use of cyclic groups, multi-signatures, and anonymous credentials strengthens the security of attribute verification and user credentials.
• Improved privacy: By utilizing anonymous credentials, the system protects user privacy by minimizing the disclosure of personal information.
• Increased trust: The multi-signature process for validating user credentials enhances trust in the system, reducing the risk of fraudulent activities.

Abstract

A system may prove one or more attributes of a user by generating cyclic groups, generating an aggregate anonymous credential by a regulatory authority and issuers of the system, setting up an issuer with a multi-signature of administrators of the system, generating user credentials, and validating an operation signed with the user credentials.

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY WITH TAPERED SIDEWALLS (17806750)

Main Inventor

Oscar van der Strate

Brief explanation

The patent application describes a memory device that uses a magnetic tunnel junction pillar. The pillar has a top portion with positive taper sidewalls and a bottom portion with negative taper sidewalls. Encapsulation layers are placed along the sidewalls of the pillar. 

• The memory device includes a magnetic tunnel junction pillar with positive and negative taper sidewalls.
• Encapsulation layers are placed along the sidewalls of the pillar.
• The encapsulation layers can be made of the same or different materials.

Potential Applications

This technology could be used in various memory devices, such as:

• Computer memory modules
• Solid-state drives (SSDs)
• Magnetic random-access memory (MRAM)
• Non-volatile memory in electronic devices

Problems Solved

The technology addresses the following problems:

• Ensuring proper encapsulation of the magnetic tunnel junction pillar
• Improving the performance and reliability of memory devices
• Enhancing the stability and durability of the memory device

Benefits

The benefits of this technology include:

• Improved memory device performance
• Enhanced reliability and durability
• Increased stability of the memory device

Abstract

A memory device includes a magnetic tunnel junction pillar extending vertically from a bottom electrode. The magnetic tunnel junction pillar includes a top portion and a bottom portion, the top portion of the magnetic tunnel junction pillar has first opposite sidewalls including a positive taper profile, while the bottom portion of the magnetic tunnel junction has second opposite sidewalls including a negative taper profile. A first encapsulation layer is disposed along the first opposite sidewalls of the top portion of the magnetic tunnel junction pillar, and a second encapsulation layer is disposed along the second opposite sidewalls of the bottom portion of the magnetic tunnel junction pillar. The first and second encapsulation layers can be made of the same or different materials.

DAMASCENE MRAM DEVICE (17806511)

Main Inventor

Koichi Motoyama

Brief explanation

The abstract describes a magnetic tunnel junction (MTJ) stack with a saw tooth edge on its vertical side surface. The stack consists of vertically aligned layers including a top electrode, a free layer, a tunneling barrier, a reference layer, and a bottom electrode. The free layer has a tapered edge, with a wider width at the upper portion and a narrower width at the lower portion.

• The MTJ stack has a saw tooth edge on its vertical side surface.
• The stack includes vertically aligned layers: top electrode, free layer, tunneling barrier, reference layer, and bottom electrode.
• The free layer has a tapered edge, with a wider width at the upper portion and a narrower width at the lower portion.

Potential applications of this technology:

• Magnetic storage devices
• Magnetic sensors
• Spintronics devices

Problems solved by this technology:

• Improved performance and efficiency of magnetic tunnel junctions
• Enhanced control over magnetic properties
• Reduction of stray magnetic fields

Benefits of this technology:

• Higher data storage density
• Faster data access and transfer rates
• Lower power consumption
• Improved reliability and durability

Abstract

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

SELECTIVE ENCAPSULATION FOR METAL ELECTRODES OF EMBEDDED MEMORY DEVICES (18455815)

Main Inventor

Ashim DUTTA

Brief explanation

The patent application describes a semiconductor device structure and a method for fabricating it. The structure includes an embedded memory device, an electrode in contact with the memory device, and a metal encapsulation layer on top of the electrode.

• The semiconductor device structure includes an embedded memory device and an electrode in contact with it.
• A metal encapsulation layer is formed on top of the electrode and a portion of its sidewalls.
• The metal encapsulation layer is made of materials that are resistant to chemical etching and conductive when oxidized.
• The method involves forming an insulating layer over the memory device and electrode.
• Portions of the insulating layer are etched to expose the top surface and sidewalls of the electrode.
• A metal encapsulation layer is then formed over and in contact with the exposed surfaces of the electrode.

Potential applications of this technology:

• Semiconductor devices with embedded memory, such as microcontrollers or memory chips.
• Integrated circuits that require a protective layer for the electrode.

Problems solved by this technology:

• Protects the electrode and embedded memory device from chemical etching.
• Provides a conductive layer for improved electrical performance.

Benefits of this technology:

• Enhanced durability and reliability of the semiconductor device.
• Improved electrical conductivity due to the conductive metal encapsulation layer.
• Simplified fabrication process for embedding memory devices.

Abstract

A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.