17806292. STACKED FIELD EFFECT TRANSISTOR simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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STACKED FIELD EFFECT TRANSISTOR

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Brent A. Anderson of Jericho VT (US)

Ruilong Xie of Niskayuna NY (US)

Albert M. Young of Fishkill NY (US)

Albert M. Chu of Nashua NH (US)

STACKED FIELD EFFECT TRANSISTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 17806292 titled 'STACKED FIELD EFFECT TRANSISTOR

Simplified Explanation

The abstract describes a semiconductor device that includes a bottom field effect transistor (FET) with a bottom source-drain epitaxial layer, a top FET stacked over the bottom FET, a back-end-of-line (BEOL) layer, a bottom gate contact that extends laterally over the bottom source-drain epitaxial layer, and a top gate contact that connects the bottom gate contact to the BEOL layer.

  • The semiconductor device includes a bottom FET and a top FET stacked on top of each other.
  • The bottom FET has a bottom source-drain epitaxial layer formed on its sides.
  • A back-end-of-line (BEOL) layer is formed on top of the top FET.
  • The bottom gate contact is in contact with the bottom FET and has an extending portion that extends laterally over the bottom source-drain epitaxial layer.
  • The top gate contact is in contact with the extending portion of the bottom gate contact and electrically connects it to the BEOL layer.

Potential Applications

  • This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be applied in power management circuits, memory devices, and microprocessors.

Problems Solved

  • The device solves the problem of integrating a bottom FET and a top FET in a compact and efficient manner.
  • It addresses the challenge of connecting the bottom gate contact to the BEOL layer.

Benefits

  • The device allows for improved performance and functionality of electronic devices.
  • It enables better power management and faster processing speeds.
  • The compact design of the device saves space and allows for more efficient circuit integration.


Original Abstract Submitted

A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

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