18452310. TRANSLATION SUPPORT FOR A VIRTUAL CACHE simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

TRANSLATION SUPPORT FOR A VIRTUAL CACHE

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Markus Helms of Boeblingen (DE)

Christian Jacobi of West Park NY (US)

Ulrich Mayer of Weil im Schoenbuch (DE)

Martin Recktenwald of Schoenaich (DE)

Johannes C. Reichart of Highland NY (US)

Anthony Saporito of Highland NY (US)

Aaron Tsai of Hyde Park NY (US)

TRANSLATION SUPPORT FOR A VIRTUAL CACHE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18452310 titled 'TRANSLATION SUPPORT FOR A VIRTUAL CACHE

Simplified Explanation

The abstract describes a virtual cache and method in a processor that supports multiple threads on the same cache line. The processor is designed to support virtual memory and multiple threads. The virtual cache directory consists of multiple directory entries, each associated with a cache line. Each cache line has a tag that includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread accessing the cache line. When a new thread determines that the cache line is valid for that thread, the validity bit for that thread is set without affecting the validity bits for other threads.

• The invention is a virtual cache and method in a processor that enables multiple threads to access the same cache line.
• The processor is capable of supporting virtual memory and multiple threads simultaneously.
• The virtual cache directory contains multiple directory entries, each corresponding to a cache line.
• Each cache line has a tag that includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread accessing the cache line.
• When a new thread accesses the cache line, it checks the validity bit for that thread and sets it if the cache line is valid for that thread.
• The validity bits for other threads remain unaffected, allowing multiple threads to access the same cache line simultaneously.

Potential Applications

• This technology can be applied in processors that support virtual memory and multiple threads.
• It can enhance the performance and efficiency of multi-threaded applications by allowing multiple threads to access the same cache line without invalidating each other's data.

Problems Solved

• The technology solves the problem of efficiently managing cache lines in processors that support virtual memory and multiple threads.
• It allows multiple threads to access the same cache line without invalidating each other's data, improving performance and reducing cache misses.

Benefits

• Improved performance and efficiency of multi-threaded applications.
• Reduced cache misses and improved cache utilization.
• Enhanced support for virtual memory and multiple threads in processors.

Original Abstract Submitted

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.