17806602. HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Tao Li of Slingerlands NY (US)

Kisik Choi of Watervliet NY (US)

Albert M. Young of Fishkill NY (US)

Julien Frougier of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17806602 titled 'HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS

Simplified Explanation

The abstract describes a semiconductor device that includes two stacked transistors and power rails on both the frontside and backside. It also includes multiple signal lines, one of which is connected to the source/drain epitaxy of the second transistor through a backside contact and an interlevel via.

  • The semiconductor device consists of two stacked transistors.
  • It has a frontside power rail connected to the first transistor's source/drain epitaxy.
  • It has a backside power rail connected to the second transistor's source/drain epitaxy.
  • The device includes multiple frontside signal lines.
  • One of the frontside signal lines is connected to the second transistor's source/drain epitaxy through a backside contact and an interlevel via.

Potential Applications

  • This semiconductor device can be used in various electronic devices and systems that require high-performance transistors.
  • It can be utilized in applications such as integrated circuits, microprocessors, memory devices, and power management systems.

Problems Solved

  • The stacked transistor design allows for increased circuit density and improved performance.
  • The use of frontside and backside power rails enables efficient power distribution.
  • The connection of signal lines through backside contacts and interlevel vias allows for better signal transmission and integration.

Benefits

  • The stacked transistor configuration provides higher integration density, allowing for more functionality in a smaller footprint.
  • The frontside and backside power rails ensure efficient power delivery, reducing power losses and improving overall performance.
  • The connection of signal lines through backside contacts and interlevel vias enhances signal integrity and reduces signal interference.


Original Abstract Submitted

Provided is a semiconductor device. The semiconductor device comprises a first transistor stacked above a second transistor. The semiconductor device further includes a frontside power rail that is electrically coupled to a source/drain epitaxy of the first transistor. The semiconductor device further includes a backside power rail that is electrically coupled to a source/drain epitaxy of the second transistor. The semiconductor device further includes a plurality of frontside signal lines. The plurality of signal lines includes a first frontside signal line that is electrically coupled to a source/drain epitaxy of the second transistor. The frontside signal line is connected to the source/drain epitaxy through a backside contact and an interlevel via.

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