Intel Corporation patent applications published on November 9th, 2023

Summary of the patent applications from Intel Corporation on November 9th, 2023

Intel Corporation has recently filed several patents related to various technologies and applications. These patents cover areas such as semiconductor devices, memory manufacturing processes, Multi-Access Edge Computing (MEC) and Operator Platform (OP) systems, wireless communication channel validation, programming flexible accelerated network pipelines, link performance predictions, secure computing environments in federated Edge Clouds, physical uplink control channel (PUCCH) designs, radio frequency circuits, electronic packages, and electrical interconnect bridges.

Summary: - Intel Corporation has filed patents related to semiconductor devices, memory manufacturing processes, MEC and OP systems, wireless communication channel validation, network pipeline programming, link performance predictions, secure computing environments, PUCCH designs, radio frequency circuits, electronic packages, and electrical interconnect bridges. - Notable applications include techniques for etching trenches through multiple layers of memory, protecting phase-change layers using amorphous silicon, coordinating MEC and EDGEAPP systems for enhanced performance, operating channel validation in wireless communication, programming network controllers based on offload hints, managing link performance predictions using algorithms and machine learning, creating secure computing environments in federated Edge Clouds, designing PUCCH for high-frequency carrier systems, and forming electronic packages with redistribution layers and interposers.

Bullet Points:

• Patents cover semiconductor devices, memory manufacturing, MEC and OP systems, wireless communication, network pipeline programming, link performance predictions, secure computing environments, PUCCH designs, radio frequency circuits, electronic packages, and electrical interconnect bridges.
• Techniques for etching trenches through memory layers and protecting phase-change layers using amorphous silicon.
• Coordination of MEC and EDGEAPP systems for improved performance in Operator Platforms.
• Operating channel validation in wireless communication using primary and secondary operating channels.
• Programming network controllers based on requested offload hints and performing packet processing.
• Managing link performance predictions using algorithms and machine learning models.
• Creating secure computing environments in federated Edge Clouds based on trust levels.
• Designing PUCCH for high-frequency carrier systems using DFT-s-OFDM waveforms.
• Radio frequency circuits with substrate connection structures and integrated front-end circuitry.
• Electronic packages with redistribution layers, interposers, and multiple communicatively coupled dies.
• Electrical interconnect bridges with multiple routing layers and vias for interconnecting different layers.

Patent applications for Intel Corporation on November 9th, 2023

APPARATUSES AND METHODS FOR ANALYZING MULTIPLE OPTICAL SIGNALS IN PARALLEL (17737067)

Main Inventor

Henry WLADKOWSKI

Brief explanation

The patent application describes an apparatus that uses optical fiber ports to input and output light through optical fiber channels. 

• The apparatus includes a spinning mask that allows a portion of the incident light to pass through based on a pattern on the mask, while blocking the remaining portion of the light.
• A photodetector is used to detect the allowed portion of the light as input signals.
• A testing device is then used to transform the input signals into the frequency domain and obtain measured signals corresponding to the optical fiber channels.
• The testing device compares the measured signals with a threshold signal to determine if there are any failures.

Abstract

An apparatus includes optical fiber ports into which optical fiber channels are input, the optical fiber channels carrying and outputting light, a mask configured to, while spinning at a frequency, allow a first portion of the light incident on the mask to pass through the mask, and block a remaining portion of the light incident on the mask, based on a pattern on the mask, and a photodetector configured to detect the allowed first portion of the light as input signals. The apparatus further includes a testing device configured to transform the input signals to a frequency domain, to obtain measured signals in frequencies respectively corresponding to the optical fiber channels, and determine whether each of the measured signals is a failure by comparing the obtained measured signals with a threshold signal.

INSPECTION TOOL AND INSPECTION METHOD (17737045)

Main Inventor

Jianyong MO

Brief explanation

The patent application describes an optical inspection tool that is used to inspect specimens with V-shaped grooves.

• The tool includes two image capture units, one directed towards the first angular surface of the groove and the other towards the second angular surface.
• The first image capture unit captures images of defects and contamination on the first angular surface, while the second image capture unit captures images of defects and contamination on the second angular surface.

Abstract

An optical inspection tool may include at least a first image capture unit and a second image capture unit for inspecting specimens having a substantially V-shaped grooves. The first image capture unit may be arranged in a first orientation so as to be directable towards a first angular surface of the V-shaped groove of each specimen. The second image capture unit may be arranged in a second orientation so as to be directable towards a second angular surface of the V-shaped groove of each specimen. The first image capture unit may be configured to capture images of defects and/or contamination on the first angular surface and the second image capture unit may be configured to capture images of defects and/or contamination on the second angular surface.

SYSTEMS, APPARATUSES, OR COMPONENTS FOR ELECTROLYTIC CORROSION PROTECTION OF ELECTRONIC ELEMENT TESTING APPARATUSES (17737047)

Main Inventor

Minh Nhat DANG

Brief explanation

The patent application describes an apparatus that includes a tester chassis, a thermal head assembly, and an electrical insulation arrangement.

• The tester chassis is connected to a chassis electric reference potential for electrostatic discharge grounding.
• The thermal head assembly is coupled to the tester chassis and has a metallic thermal contact surface.
• The electrical insulation arrangement is placed between the metallic thermal contact surface and the chassis electric reference potential to prevent electrical contact between them.
• The purpose of this arrangement is to protect the metallic thermal contact surface from electrolytic corrosion.
• The patent application also mentions an electrolytic corrosion protection system for the apparatus and a cable assembly for the apparatus.

Abstract

An apparatus comprises a tester chassis connected to a chassis electric reference potential for electrostatic discharge grounding of the tester chassis; a thermal head assembly coupled to the tester chassis, the thermal head assembly having a metallic thermal contact surface; and an electrical insulation arrangement disposed between the metallic thermal contact surface and the chassis electric reference potential to electrically insulate the metallic thermal contact from the chassis electric reference potential. An electrolytic corrosion protection system for the apparatus and a cable assembly for the apparatus.

APPARATUS AND METHOD FOR PROTECTING PROBE CARD AND PROBES USING THERMAL HEAT SENSOR TRACE (17737042)

Main Inventor

Arthur ISAKHAROV

Brief explanation

- The patent application describes an apparatus that includes a thermal heat sensor trace and a controller.

- The thermal heat sensor trace is made of conductive metal and is placed in a space transformer. - The sensor trace is designed to form a resistance, and the controller can measure the voltage across this resistance. - The voltage measured by the controller is directly related to the temperature of the space transformer. - The controller is programmed to compare the measured voltage to a predetermined threshold voltage. - If the measured voltage is equal to or greater than the threshold voltage, the controller will output an alert signal. - The alert signal can be used to reduce or warn about the temperature of the space transformer.

Abstract

An apparatus includes a thermal heat sensor trace including conductive metal and disposed in a space transformer, the thermal heat sensor trace being configured to form a resistance, and a controller configured to sense a voltage across the resistance formed by the thermal heat sensor trace, the voltage positively correlating to a temperature of the space transformer. The controller is further configured to determine whether the sensed voltage is greater than or equal to a predetermined threshold voltage, and based on the sensed voltage being determined to be greater than or equal to the predetermined threshold voltage, output an alert signal for reducing and/or warning of the temperature of the space transformer.

REDUCED BRIDGE STRUCTURE FOR A PHOTONIC INTEGRATED CIRCUIT (17740068)

Main Inventor

Chia-Pin Chiu

Brief explanation

- The patent application describes a reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit that includes a ring resonator structure.

- The reduced bridge structure is designed to minimize the number of bridges around the micro-ring structure of the ring resonator structure. - The architecture includes an optical and electrical routing arrangement to achieve this reduction in bridges. - One bridge portion is reserved for use as a signal trace, which is not routed over a silicon waveguide. - By avoiding the routing of the signal trace over a silicon waveguide, potential interference between the radio frequency (RF) signal on the trace and optical communication in the waveguide is prevented. - The innovation aims to improve the performance and reliability of the integrated circuit by reducing interference and optimizing signal transmission.

Abstract

A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

SYSTEM AND PROCESS FOR CLEANING A MEMBRANE (17738024)

Main Inventor

Safak SAYAN

Brief explanation

- The patent application is for a membrane cleaning system and process.

- The system includes a membrane holder that holds a membrane in a cut-out section. - The cut-out section allows access to the membrane from two opposing sides. - The system also includes a speaker that emits sound waves at a resonant frequency of the membrane. - The sound waves are directed to one side of the membrane. - The sound waves are emitted for a predetermined duration and at a predetermined amplitude. - The purpose of the system is to clean the membrane using sound waves.

Abstract

The present disclosure is directed to a membrane cleaning system and a membrane cleaning process, the membrane cleaning system including: a membrane; a membrane holder accommodating the membrane in a cut-out section within the membrane holder, wherein the cut-out section allows access to the membrane from two opposing sides; and a speaker configured to emit sound waves of a resonant frequency of the membrane for a predetermined duration and at a predetermined amplitude, wherein the sound waves are directed to one side of the membrane.

CURRENT CONTROL FOR A MULTICORE PROCESSOR (18353790)

Main Inventor

Alexander Gendler

Brief explanation

- This patent application is about a technology related to current control for a multicore processor.

- The multicore processor includes multiple analog current comparators that measure the current utilization of each core. - The processor has the ability to individually throttle the cores based on the measurements from the analog current comparators. - A memory device in the multicore processor stores instructions that allow power management agents to determine whether to send throttle requests based on the historical current measurements of the cores.

Abstract

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

COMPUTER-ASSISTED OR AUTONOMOUS DRIVING VEHICLES SOCIAL NETWORK (18352224)

Main Inventor

Fatema Adenwala

Brief explanation

- The patent application is related to computer-assisted or autonomous driving (CA/AD) vehicles.

- It discloses apparatuses, methods, and storage medium associated with CA/AD vehicles. - CA/AD vehicles can be part of a CA/AD vehicle social network (CASN). - In CASN, CA/AD vehicles can form connections or relationships with each other. - CA/AD vehicles with existing connections can share CASN information with each other. - CASN information may include authenticated and/or proprietary information. - The patent application also mentions other embodiments that are described and claimed.

Abstract

Apparatuses, methods and storage medium associated with computer-assisted or autonomous driving (CA/AD) vehicles are disclosed herein. In embodiments, CA/AD vehicles are members of a CA/AD vehicle social network (CASN) in which various CA/AD vehicles may form connections or relationships with one another. CA/AD vehicles that have an existing relationship or connection may share CASN information with one another. The CASN information may include authenticated and/or proprietary information. Other embodiments are also described and claimed.

COMPUTE OPTIMIZATIONS FOR NEURAL NETWORKS (18315625)

Main Inventor

Kevin Nealis

Brief explanation

The abstract describes a compute apparatus that can execute instructions for neural networks efficiently. 

• The compute apparatus has a decode unit that can decode a single instruction into multiple operands, including a multi-bit input value and a one-bit weight associated with a neural network.
• The arithmetic logic unit in the compute apparatus includes a multiplier, an adder, and an accumulator register.
• To execute the decoded instruction, the multiplier performs a fused operation that combines an exclusive not OR (XNOR) operation and a population count operation.
• The adder adds the intermediate product from the multiplier to a value stored in the accumulator register and updates the value stored in the accumulator register.

Abstract

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

STACK ACCESS THROTTLING FOR SYNCHRONOUS RAY TRACING (17589689)

Main Inventor

PAWEL MAJEWSKI

Brief explanation

The patent application describes an apparatus and method for managing stack access in synchronous ray tracing.

• The apparatus includes ray tracing acceleration hardware that controls the allocation of active ray tracing stacks.
• The goal is to ensure that the size of active ray tracing stack allocations does not exceed a certain threshold.
• An execution unit executes a thread that can request a new ray tracing stack allocation from the hardware.
• The hardware will only permit the new allocation if it will not cause the size of active allocations to exceed the threshold.

Abstract

Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.

DYNAMIC LOAD BALANCING OF COMPUTE ASSETS AMONG DIFFERENT COMPUTE CONTEXTS (18195230)

Main Inventor

James VALERIO

Brief explanation

This patent application describes a method for allocating commands from multiple sources to different segments of a processing device. 

• The processing device can be divided into multiple portions, and each portion is assigned to process commands from a specific source.
• If there is only one source providing commands, the entire processing device is allocated to process commands from that source.
• When a second source provides commands, some segments of the processing device are allocated to process commands from the first source, while other segments are allocated to process commands from the second source.
• This allows for the execution of commands from multiple applications simultaneously on a processing unit.

Abstract

Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

TECHNOLOGIES FOR HIERARCHICAL CLUSTERING OF HARDWARE RESOURCES IN NETWORK FUNCTION VIRTUALIZATION DEPLOYMENTS (18195314)

Main Inventor

Andrey Chilikin

Brief explanation

- The patent application describes technologies for organizing and managing hardware resources in network function virtualization (NFV) deployments.

- A compute node is used to create a network function profile, which includes a list of network functions that need to be deployed on the compute node. - The compute node then translates this network function profile into a hardware profile for each interconnected hardware resource. - The compute node deploys the network functions to the appropriate hardware resources based on the hardware profile. - This technology allows for efficient and optimized allocation of network functions to hardware resources in NFV deployments. - It helps in managing and organizing the hardware resources in a hierarchical manner. - The patent application mentions that there may be other embodiments or variations of this technology.

Abstract

Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.

SYSTEM AND METHOD FOR GRANULAR RESET MANAGEMENT WITHOUT REBOOT (18312759)

Main Inventor

Bharat S. PILLILLI

Brief explanation

The patent application describes a system for managing resets in a computer system without the need for a complete system reboot.

• The system includes a subsystem and a processor with a reset management circuit.
• The reset management circuit receives a command to reset the subsystem.
• It determines if the subsystem can be reset without rebooting the entire system.
• If it can, the circuit blocks the use of the subsystem, drains it, and then resets it.
• The patent also covers the circuitry and method used in this system.

Abstract

A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

IN-NETWORK COLLECTIVE OPERATIONS (18222946)

Main Inventor

Vivek KASHYAP

Brief explanation

This patent application describes a switch that is used in training machine learning models.

• The switch uses a reliable transport protocol to receive packet communications from worker nodes involved in the collective operation.
• The switch stores the receipt state of each packet received from the worker nodes.
• The switch then uses a non-reliable transport protocol to send the packets to a device responsible for aggregating the results.
• The reliable transport protocol used by the switch is different from the non-reliable transport protocol.

Abstract

Examples described herein relate to a switch comprising circuitry configured to for packet communications associated with a collective operation to train machine learning (ML) models: utilize a reliable transport protocol for communications from at least one worker node of the collective operation to a switch, wherein the utilize a reliable transport protocol for communications from at least one worker node of the collective operation to the switch comprises store packet receipt state for per-packet communications from the at least one worker node of the collective operation to the switch and utilize a non-reliable transport protocol by the switch to a device that is to perform aggregation of results, wherein the reliable transport protocol comprises a different protocol than that of the non-reliable transport protocol.

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers (18222989)

Main Inventor

Jack Z. Yinger

Brief explanation

The patent application describes a method and architecture for efficiently implementing a matrix multiplication systolic array in integrated circuits.

• The systolic array architecture includes a processing element array, a column feeder array, and a row feeder array.
• The architecture reduces the bandwidth of external memory by interleaving the matrix data through a feeding pattern of the column feeder array and the row feeder array.
• The method and architecture aim to improve the efficiency of matrix multiplication operations in integrated circuits.
• The innovation provides a solution for implementing a generic matrix multiplier (SGEMM) in integrated circuits.
• The systolic array feed methods and related processing element microarchitectures optimize the performance of the matrix multiplication systolic array.
• The reduction in external memory bandwidth improves the overall efficiency and speed of matrix multiplication operations.
• The patent application provides a detailed description of the systolic array architecture and its components, offering a practical solution for implementing matrix multiplication in integrated circuits.

Abstract

Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.

COMPUTING DEVICES WITH SECURE BOOT OPERATIONS (18223399)

Main Inventor

Yeluri Raghuram

Brief explanation

This patent application relates to security measures in cloudlet environments. It describes a computing device, known as a cloudlet, that includes various components to enhance security. 

• The cloudlet includes a trusted execution environment, which is a secure area where sensitive operations can be performed.
• It also includes a Basic Input/Output System (BIOS) that can request a Key Encryption Key (KEK) from the trusted execution environment.
• The cloudlet further includes a Self-Encrypting Storage (SES) that is associated with the KEK.
• The trusted execution environment verifies the BIOS and provides the KEK to the BIOS after verification.
• The BIOS then uses the KEK to unlock the SES, allowing the trusted execution environment to access it.

Overall, this patent application describes a system where the trusted execution environment and BIOS work together to enhance security in a cloudlet environment by utilizing encryption keys and secure storage.

Abstract

Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.

METHODS AND APPARATUS FOR DISCRIMINATIVE SEMANTIC TRANSFER AND PHYSICS-INSPIRED OPTIMIZATION OF FEATURES IN DEEP LEARNING (18142997)

Main Inventor

Anbang YAO

Brief explanation

The patent application describes methods and apparatus for improving deep learning algorithms by combining discriminative semantic transfer and physics-inspired optimization techniques.

• The method involves training a convolutional neural network (CNN) using a sequence of training images.
• The CNN is divided into two stages: the first stage receives the training images and generates a semantic segmentation mask to describe objects in a cluttered scene.
• The second stage receives the semantic segmentation mask and produces semantic features.
• The weights from the first stage are used as feature extractors, while the weights from the second stage act as classifiers.
• By utilizing these weights, the algorithm can identify edges in the cluttered scene using the semantic features.
• The combination of discriminative semantic transfer and physics-inspired optimization helps improve the accuracy and efficiency of deep learning algorithms.

Abstract

Methods and apparatus for discrimitive semantic transfer and physics-inspired optimization in deep learning are disclosed. A computation training method for a convolutional neural network (CNN) includes receiving a sequence of training images in the CNN of a first stage to describe objects of a cluttered scene as a semantic segmentation mask. The semantic segmentation mask is received in a semantic segmentation network of a second stage to produce semantic features. Using weights from the first stage as feature extractors and weights from the second stage as classifiers, edges of the cluttered scene are identified using the semantic features.

METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO RE-PARAMETERIZE MULTIPLE HEAD NETWORKS OF AN ARTIFICIAL INTELLIGENCE MODEL (18312584)

Main Inventor

Vinnam Kim

Brief explanation

The patent application describes a method and apparatus for re-parameterizing multiple head networks of an artificial intelligence (AI) model. 

• The invention involves training an AI model using both labeled data and pseudo-labeled data.
• The AI model includes multiple head networks.
• After the AI model has been trained, the invention re-parameterizes only the multiple head networks into a fully connected layer.
• Other portions of the AI model are not re-parameterized.
• This re-parameterization process helps optimize the performance of the AI model.
• The invention provides a more efficient and effective way to re-parameterize multiple head networks in an AI model.

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed re-parameterize multiple head networks of an artificial intelligence model. An example apparatus is to train an AI model using labeled data and pseudo-labeled data, the AI model including multiple head networks. Additionally, the example apparatus is to, after the AI model has been trained, re-parameterize the multiple head networks of the AI model into a fully connected layer without re-parameterizing other portions of the AI model.

MULTI-PLANE IMAGE COMPRESSION (17926532)

Main Inventor

Scott JANUS

Brief explanation

The patent application describes methods and systems for compressing multi-plane images (MPI).

• MPI compression techniques are disclosed in the patent application.
• The techniques involve accessing an input multiplane image stack from a source camera viewpoint.
• The input stack includes texture images and corresponding alpha images representing transparency.
• The disclosed apparatus includes a compressed image encoder to convert the texture images or alpha images into a single composite image.
• The resulting compressed multiplane image stack is generated.
• The interface is used to output the compressed multiplane image stack.

Abstract

Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.

GRAPHICS ARCHITECTURE INCLUDING A NEURAL NETWORK PIPELINE (18310015)

Main Inventor

HUGUES LABBE

Brief explanation

The patent application describes a graphics processor with a programmable neural network unit.

• The graphics processor includes execution resources, cache memory, and a cache memory prefetcher.
• The programmable neural network unit has circuitry to perform neural network operations and activation operations for a layer of a neural network.
• The programmable neural network unit can be accessed by cores within the graphics processor.
• The neural network hardware block within the programmable neural network unit is configured to determine a prefetch pattern for the cache memory prefetcher.

Abstract

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

DEPOSITION TOOL AND METHOD FOR FILLING DEEP TRENCHES (17738028)

Main Inventor

Elijah V. KARPOV

Brief explanation

The patent application describes a semiconductor deposition tool that includes a specimen support, ion guns, sources, and electron beam guns.

• The electron beam guns, sources, and ion beam guns are positioned below the specimen support, with the specimen facing downward.
• The method involves using the electron beam gun to deposit source material in a trench on the specimen and adjacent surfaces.
• The ion beam gun is then activated to remove portions of the deposited source material on the surfaces adjacent to the trench opening.

Abstract

The present disclosure is directed to semiconductor deposition tools having a specimen support, at least one ion gun directed to a specimen positioned on the specimen support, at least one source, and at least one electron beam gun directed at the source. In an aspect, the electron beam guns, sources, and ion beam guns are positioned below the specimen support and specimen positioned thereon, which has its top surface facing downward. In another aspect, the method includes activating the electron beam gun and depositing the source material in a trench in the specimen and on surfaces adjacent to the opening of the trench and activating the ion beam gun to remove portions of the source material deposited on the surfaces adjacent to the opening of the trench.

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME (18221754)

Main Inventor

Oleg GOLONZKA

Brief explanation

The patent application describes gate aligned contacts and methods of forming them in a semiconductor structure. 

• Gate aligned contacts are formed by placing contact plugs directly between the sidewall spacers of adjacent gate structures.
• The gate structures consist of a gate dielectric layer, a gate electrode, and sidewall spacers.
• The contact plugs and contacts are formed after the gate structures are created.
• This method allows for efficient and precise formation of gate aligned contacts in a semiconductor structure.

Abstract

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS (18223981)

Main Inventor

Sridhar GOVINDARAJU

Brief explanation

- The patent application describes techniques and configurations to reduce transistor gate short defects.

- One method involves forming multiple lines, where each line contains a gate electrode material. - An electrically insulative material is then deposited to fill the spaces between the lines. - Afterward, a portion of at least one line is removed to isolate the gate electrode material of one transistor device from another. - The purpose of this method is to prevent short circuits between the gate electrode materials of different transistor devices. - The patent application suggests that other embodiments and variations of the method may also be described and claimed.

Abstract

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER (18222855)

Main Inventor

Debendra MALLIK

Brief explanation

- The patent application describes a multi-chip unit for chip-level packaging.

- The unit includes multiple IC chips that are interconnected through a metal redistribution structure. - The IC chips are directly bonded to an integrated heat spreader, eliminating the need for thermal interface material. - This direct bonding reduces the bond line thickness and thermal resistance. - The integrated heat spreader also serves as a structural member of the unit. - The second side of the redistribution structure can be interconnected to a host using solder interconnects. - A sacrificial interposer is used to planarize IC chips of different thicknesses before bonding the heat spreader. - The sacrificial interposer can be removed to expose the redistribution layer for further interconnection to a substrate without through-substrate vias.

Abstract

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

DESIGN OPTIMIZATION FOR RASTER SCANNING (17738085)

Main Inventor

Vinith BEJUGAM

Brief explanation

The patent application is about a method and system for creating structures on a glass substrate using a pulsed laser tool. 

• The method involves using a pulsed laser tool to create a line-shaped modification on the glass substrate.
• The laser tool moves in a predetermined pattern, with single steps in one direction and plural lateral steps in a perpendicular direction.
• This pattern is repeated to create an assembly of line-shaped modifications in parallel rows on the glass substrate.
• The structures are then formed from these parallel rows of line-shaped modifications.

Abstract

The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING (18216040)

Main Inventor

Bok Eng CHEAH

Brief explanation

The patent application describes an electronic device with an integrated circuit (IC) die.

• The IC die has a first bonding pad surface and a first backside surface.
• A first active device layer is located between the first bonding pad surface and the first backside surface.
• The device includes at least one stacked through silicon via (TSV) between the first backside surface and the first bonding pad surface.
• The stacked TSV includes a first buried silicon via (BSV) portion with a larger width and a second BSV portion with a smaller width.
• The first BSV portion extends to the first backside surface, while the second BSV portion extends to the first active device layer.

Abstract

An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

ELECTRICAL INTERCONNECT BRIDGE (18224504)

Main Inventor

Srinivas V. PIETAMBARAM

Brief explanation

- The patent application is about a technology called electrical interconnect bridge.

- The electrical interconnect bridge is made of a mold compound material called bridge substrate. - The bridge substrate contains multiple routing layers, each with fine line and space (FLS) traces. - The bridge also includes a via, which is a connection that goes through the substrate. - The via allows the FLS traces in one routing layer to be electrically connected to the FLS traces in another routing layer. - The purpose of this technology is to provide a means for connecting different routing layers within the bridge substrate. - The technology can be used in various electrical applications where interconnecting different layers is required.

Abstract

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS (18224794)

Main Inventor

Srinivas PIETAMBARAM

Brief explanation

- The patent application describes electronic packages and methods of forming them.

- The package includes a redistribution layer (RDL) and an interposer. - A glass core is formed over the RDL and surrounds the interposer. - The package also includes multiple dies that are communicatively coupled with the interposer.

Abstract

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

DISTRIBUTED RADIOHEAD SYSTEM (18029932)

Main Inventor

Jayprakash THAKUR

Brief explanation

- The patent application describes a radio frequency circuit that includes a substrate with a radio frequency front-end to antenna connector.

- The RF FE-to-Ant connector consists of a conductor track structure and a substrate connection structure. - The substrate also contains integrated radio frequency front-end circuitry. - The substrate connection structure can be solderable, weldable, or adherable. - It forms a radio frequency signal interface with an antenna circuit connection structure of an external substrate. - The substrate has an edge region where the substrate connection structure is located.

Abstract

In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.

PHYSICAL UPLINK CONTROL CHANNEL DESIGN FOR DISCRETE FOURIER TRANSFORM-SPREAD-ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING (DFT-S-OFDM) WAVEFORMS (18347247)

Main Inventor

Gang Xiong

Brief explanation

The patent application discusses designs for physical uplink control channel (PUCCH) in systems operating above the 52.6 GHz carrier frequency using discrete Fourier transform-spread-orthogonal frequency-division multiplexing (DFT-s-OFDM) waveforms. 

• The embodiments provide designs for PUCCH in DFT-s-OFDM waveforms for systems operating above 52.6 GHz carrier frequency.
• The designs focus on phase tracking reference signal (PT-RS) for PUCCH in high-frequency carrier systems.
• The patent application also mentions other undisclosed embodiments related to the topic.

Abstract

Various embodiments herein provide physical uplink control channel (PUCCH) designs for discrete Fourier transform-spread-orthogonal frequency-division multiplexing (DFT-s-OFDM) waveforms for systems operating above the 52.6 GHz carrier frequency. Some embodiments of the present disclosure may be directed to phase tracking reference signal (PT-RS) design for PUCCH with carrier frequencies above 52.6 GHz. Other embodiments may be disclosed and/or claimed.

SECURE APPLICATION COMPUTING ENVIRONMENT IN A FEDERATED EDGE CLOUD (18223887)

Main Inventor

Dario Sabella

Brief explanation

The patent application describes a system and method for creating a secure computing environment in a federated Edge Cloud.

• The system receives application information from an application provider.
• The application information is processed in a secure environment on a device, such as an edge computing node.
• A trust level is assigned to the application based on the application information.
• Based on the trust level, a trusted platform is selected to deploy or launch the application.
• The system ensures that the application is executed in a secure and trusted environment.
• This innovation improves the security and reliability of applications in a federated Edge Cloud.

Abstract

Systems and methods for a secure application computing environment in a federated Edge Cloud are disclosed herein. Application information corresponding to an application from an application provider may be received in a secure environment of a device such as an edge computing node. A trust level for execution of the application may be associated based at least in part on the application information, and based on the associated trust level, a trusted platform may be selected to deploy or launch the application.

LINK PERFORMANCE PREDICTION TECHNOLOGIES (18356423)

Main Inventor

Jonas Svennebring

Brief explanation

The present disclosure is about Link Performance Predictions (LPPs) used in managing radio communication links. LPPs predict future network behaviors/metrics such as bandwidth, latency, capacity, and coverage holes.

• LPPs are used to improve signaling and link resource utilization in network nodes.
• The link performance analysis is divided into multiple layers, each determining its own link performance metrics.
• Different algorithms and machine learning models are used in each layer to provide results.
• The results from each layer are fused together by an LPP layer/engine to obtain the final LPP.
• The LPPs are then communicated to network nodes for operational decision-making.
• The patent application describes other embodiments and claims related to the invention.

Abstract

The present disclosure is related to Link Performance Predictions (LPPs), which are used in connection with management of radio communication links. The LPPs are predictions of future network behaviors/metrics (e.g., bandwidth, latency, capacity, coverage holes, and/or the like). The LPPs are communicated to network nodes, which allows the network nodes to make operational decisions for improved signaling/link resource utilization. The link performance analysis is divided into multiple layers that determine their own link performance metrics, which are then fused together to make an LPP. Each layer runs different algorithms and/or machine learning models, and provides respective results to an LPP layer/engine that fuses the results together to obtain the LPP. Other embodiments are described and/or claimed.

TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF (18213514)

Main Inventor

Peter P. WASKIEWICZ, JR.

Brief explanation

- The patent application is about technologies for programming flexible accelerated network pipelines.

- It involves a computing device with a network controller that can process network packets with various offloads. - The computing device loads a program binary file that includes a packet processing program and a requested hint section. - The binary file may be in the form of an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. - The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller accordingly. - The network controller performs offloads such as packet classification, hashing, checksums, traffic shaping, and returns the results as hints in metadata. - The packet processing program then takes actions based on the metadata, such as forwarding, dropping, packet modification, etc. - The computing device can compile an eBPF source file to generate the binary file. - The patent application also mentions that there are other embodiments described and claimed.

Abstract

Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

OPERATING CHANNEL VALIDATION UNDER PROTECTED BEACON (18352189)

Main Inventor

Ido Ouzieli

Brief explanation

The patent application describes a system for operating channel validation in wireless communication.

• A device connects to an access point (AP) and establishes a primary operating channel for communication.
• The device receives a protected beacon frame from the AP, which contains information about a secondary operating channel.
• The device extracts the secondary operating channel from the protected beacon frame.
• Based on the primary and secondary operating channels, the device determines its association status with the AP.

Abstract

This disclosure describes systems, methods, and devices related to operating channel validation. A device may associate with an access point (AP). The device may establish a first operating channel to communicate with the AP. The device may identify a protected beacon frame received from the AP, wherein the protected beacon frame comprises an indication of a second operating channel. The device may extract the second operating channel from the protected beacon frame. The device may determine an association status with the AP based on the first operating channel and the second operating channel.

OPERATOR PLATFORM INSTANCE FOR MEC FEDERATION TO SUPPORT NETWORK-AS-A-SERVICE (18216257)

Main Inventor

Dario Sabella

Brief explanation

- The patent application discusses various approaches for Multi-Access Edge Computing (MEC) and Operator Platform (OP) systems and how to manage applications and services in such systems.

- The example system described in the patent application is designed to coordinate the operations of a MEC system and an EDGEAPP system. - The system focuses on performing lifecycle management (LCM) operations of MEC and EDGEAPP applications in an Operator Platform instance within an Operator Platform domain. - By enabling coordination between MEC and EDGEAPP applications in their respective systems, the system enhances the overall performance of an Operator Platform. - The system receives application data from an application client associated with either the MEC system or the EDGEAPP system. - The received application data is then transmitted to an application host associated with the other system. - This enables the system to facilitate the lifecycle management of respective apps and facilitate communication between MEC and EDGEAPP systems.

Abstract

Various approaches for Multi-Access Edge Computing (MEC) and Operator Platform (OP) systems, and management of applications and services in such systems, are discussed herein. An example system is configured to coordinate operations of a MEC system and an EDGEAPP system. The system performs lifecycle management (LCM) operations of MEC and EDGEAPP applications in an Operator Platform instance in an Operator Platform domain, enabling coordination of the MEC and EDGEAPP applications in their respective systems. The system receives application data from an application client of a user equipment (UE) associated with either the MEC system or the EDGEAPP system and transmits the application data to an application host associated with (e.g., executed on) the other system. The system thus enables LCM of respective apps and communications among MEC and EDGEAPP systems, enhancing the overall performance of an Operator Platform.

TECHNOLOGIES FOR SEMICONDUCTOR DEVICES INCLUDING AMORPHOUS SILICON (17735529)

Main Inventor

Luca Fumagalli

Brief explanation

- The patent application is about techniques for semiconductor devices, specifically those using amorphous silicon.

- The application describes a method of etching trenches through multiple layers of a memory, including a phase-change layer, during the manufacturing process. - To protect the phase-change layer during subsequent processing steps, amorphous silicon is applied to it using low-temperature chemical vapor deposition. - This application of amorphous silicon is done without exceeding the melting point of the phase-change layer. - The amorphous silicon can then be oxidized, creating a silicon oxide layer that acts as a protective barrier around the phase-change layer.

Abstract

Techniques for semiconductor devices including amorphous silicon are disclosed. In the illustrative embodiment, trenches are etched through several layers of a memory during manufacture, including through a phase-change layer. To protect the phase-change layer during further processing steps, amorphous silicon is applied to the phase-change layer using low-temperature chemical vapor deposition, which can be done without exceeding the melting point of the phase-change layer. The amorphous silicon can be oxidized, forming a protective silicon oxide layer around the phase-change layer.