US Patent Application 18222989. Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers simplified abstract
Contents
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Organization Name
Inventor(s)
Jack Z. Yinger of San Jose CA (US)
Tomasz Czajkowski of Toronto (CA)
Davor Capalija of Toronto (CA)
Eriko Nurvitadhi of San Jose CA (US)
Deborah Marr of San Jose CA (US)
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers - A simplified explanation of the abstract
This abstract first appeared for US patent application 18222989 titled 'Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Simplified Explanation
The patent application describes a method and architecture for efficiently implementing a matrix multiplication systolic array in integrated circuits.
- The systolic array architecture includes a processing element array, a column feeder array, and a row feeder array.
- The architecture reduces the bandwidth of external memory by interleaving the matrix data through a feeding pattern of the column feeder array and the row feeder array.
- The method and architecture aim to improve the efficiency of matrix multiplication operations in integrated circuits.
- The innovation provides a solution for implementing a generic matrix multiplier (SGEMM) in integrated circuits.
- The systolic array feed methods and related processing element microarchitectures optimize the performance of the matrix multiplication systolic array.
- The reduction in external memory bandwidth improves the overall efficiency and speed of matrix multiplication operations.
- The patent application provides a detailed description of the systolic array architecture and its components, offering a practical solution for implementing matrix multiplication in integrated circuits.
Original Abstract Submitted
Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.
