US Patent Application 18216040. MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING simplified abstract
Contents
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
Organization Name
Inventor(s)
Bok Eng Cheah of Bukit Gambir (MY)
Choong Kooi Chee of Batu Uban (MY)
Jackson Chung Peng Kong of Tanjung Tokong (MY)
Wai Ling Lee of Bayan Lepas (MY)
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18216040 titled 'MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
Simplified Explanation
The patent application describes an electronic device with an integrated circuit (IC) die.
- The IC die has a first bonding pad surface and a first backside surface.
- A first active device layer is located between the first bonding pad surface and the first backside surface.
- The device includes at least one stacked through silicon via (TSV) between the first backside surface and the first bonding pad surface.
- The stacked TSV includes a first buried silicon via (BSV) portion with a larger width and a second BSV portion with a smaller width.
- The first BSV portion extends to the first backside surface, while the second BSV portion extends to the first active device layer.
Original Abstract Submitted
An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.