US Patent Application 18223981. TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS simplified abstract

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

Organization Name

Intel Corporation

Inventor(s)

Sridhar Govindaraju of Hillsboro OR (US)

Matthew J. Prince of Portland OR (US)

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18223981 titled 'TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

Simplified Explanation

- The patent application describes techniques and configurations to reduce transistor gate short defects. - One method involves forming multiple lines, where each line contains a gate electrode material. - An electrically insulative material is then deposited to fill the spaces between the lines. - Afterward, a portion of at least one line is removed to isolate the gate electrode material of one transistor device from another. - The purpose of this method is to prevent short circuits between the gate electrode materials of different transistor devices. - The patent application suggests that other embodiments and variations of the method may also be described and claimed.

Original Abstract Submitted

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.