Category:Chiao-Ti Huang of Portland OR US
Chiao-Ti Huang
Chiao-Ti Huang from Portland OR US has applied for patents in technology areas such as H01L23/522, H01L23/528 with intel corporation.
Patents
Pages in category "Chiao-Ti Huang of Portland OR US"
The following 28 pages are in this category, out of 28 total.
1
- 18370287. INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS (Intel Corporation)
- 18372506. INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS (Intel Corporation)
- 18374600. TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER (INTEL CORPORATION)
- 18374607. MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL LAYOUT EFFECT TUNING (INTEL CORPORATION)
- 18375064. INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACERS FOR 2D CHANNEL MATERIALS (INTEL CORPORATION)
- 18375084. INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING (INTEL CORPORATION)
- 18469810. VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING (Intel Corporation)
- 18471705. AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT (Intel Corporation)
- 18471710. DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS (Intel Corporation)
- 18477947. METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE (INTEL CORPORATION)
- 18498318. INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS (Intel Corporation)
- 18498340. INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES (Intel Corporation)
2
I
- Intel corporation (20250006733). INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENTIAL EPITAXIAL SOURCE OR DRAIN DENT
- Intel corporation (20250006734). PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH
- Intel corporation (20250096114). VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
- Intel corporation (20250098260). INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
- Intel corporation (20250107156). DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
- Intel corporation (20250107175). INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Intel corporation (20250107212). AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
- Intel corporation (20250112120). INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Intel corporation (20250113547). INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACERS FOR 2D CHANNEL MATERIALS
- Intel corporation (20250113559). TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER
- Intel corporation (20250113595). MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL LAYOUT EFFECT TUNING
- Intel corporation (20250113600). METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE
- Intel corporation (20250140649). INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
- Intel corporation (20250142948). INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS
