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18477947. METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE (INTEL CORPORATION)

From WikiPatents

METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE

Organization Name

INTEL CORPORATION

Inventor(s)

Yulia Gotlib of Hillsboro OR US

Matthew J. Prince of Portland OR US

Sachin S. Vaidya of Portland OR US

Ying Zhou of Portland OR US

Xiaoye Qin of Portland OR US

Ryan Pearce of Beaverton OR US

Andrew Arnold of Hillsboro OR US

Chiao-Ti Huang of Portland OR US

METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE

This abstract first appeared for US patent application 18477947 titled 'METAL GATE CUT WITH REDUCED OXIDATION AND PARASITIC CAPACITANCE

Original Abstract Submitted

Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

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