20250176255. Back-side Nanoribbon Removal (Intel)
BACK-SIDE NANORIBBON REMOVAL
Abstract: fabrication methods for integrated circuit (ic) structures and devices involving back-side nanoribbon removal are described herein. in one example, back-side nanoribbon removal involves providing stacks of nanoribbons from a first side of an ic structure, followed by removing one or more of the nanoribbons from a second side that is opposite the first side. in one example, an ic structure fabricated with back-side nanoribbon removal techniques may include a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where the number of nanoribbons in the first stack is less than in the second stack. a first transistor includes first channel regions in the nanoribbons of the first stack and a second transistor includes second channel regions in the nanoribbons of the second stack. therefore, in one such example, the first transistor has channel regions in fewer nanoribbons than the second transistor.
Inventor(s): Chiao-Ti Huang, Tao Chu, Guowei Xu, Robin Chao, Kan Zhang, Yang Zhang, Ting-Hsiang Hung, Feng Zhang, Anand S. Murthy, Tahir Ghani
CPC Classification: H10D84/83 (No explanation available)
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- Patent Applications
- Intel Corporation
- CPC H10D84/83
- Chiao-Ti Huang of Portland OR US
- Tao Chu of Portland OR US
- Guowei Xu of Portland OR US
- Robin Chao of Portland OR US
- Kan Zhang of HILLSBORO OR US
- Yang Zhang of Rio Rancho NM US
- Ting-Hsiang Hung of Beaverton OR US
- Feng Zhang of Hillsboro OR US
- Anand S. Murthy of Portland OR US
- Tahir Ghani of Portland OR US