Intel corporation (20250096114). VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
Organization Name
Inventor(s)
Chiao-Ti Huang of Portland OR US
Ting-Hsiang Hung of Beaverton OR US
Chia-Ching Lin of Portland OR US
Yang Zhang of Rio Rancho NM US
Anand Murthy of Portland OR US
Conor P. Puls of Portland OR US
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
This abstract first appeared for US patent application 20250096114 titled 'VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
Original Abstract Submitted
techniques to form semiconductor devices can include one or more via structures having substrate taps. a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). the gate structure may extend over the semiconductor regions of any number of devices along a given direction. the gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. the via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. the conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. the via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.
- Intel corporation
- Robin Chao of Portland OR US
- Chiao-Ti Huang of Portland OR US
- Guowei Xu of Portland OR US
- Ting-Hsiang Hung of Beaverton OR US
- Tao Chu of Portland OR US
- Feng Zhang of Hillboro OR US
- Chia-Ching Lin of Portland OR US
- Yang Zhang of Rio Rancho NM US
- Anand Murthy of Portland OR US
- Conor P. Puls of Portland OR US
- H01L23/522
- H01L23/528
- CPC H01L23/5226