20250169130. Integrated Circuit Structure (Intel)
INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES
Abstract: fabrication methods for integrated circuit (ic) structures and devices with different nanoribbon thicknesses are disclosed. in one example, an ic structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.
Inventor(s): Tao Chu, Minwoo Jang, Yanbin Luo, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin, Yang Zhang, Kan Zhang, Chung-Hsun Lin, Anand S. Murthy
CPC Classification: H10D62/118 (No explanation available)
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- Patent Applications
- Intel Corporation
- CPC H10D62/118
- Tao Chu of Portland OR US
- Minwoo Jang of Portland OR US
- Yanbin Luo of Portland OR US
- Paul Packan of Hillsboro OR US
- Guowei Xu of Portland OR US
- Chiao-Ti Huang of Portland OR US
- Robin Chao of Portland OR US
- Feng Zhang of Hillsboro OR US
- Ting-Hsiang Hung of Beaverton OR US
- Chia-Ching Lin of Portland OR US
- Yang Zhang of Rio Rancho NM US
- Kan Zhang of HILLSBORO OR US
- Chung-Hsun Lin of Portland OR US
- Anand S. Murthy of Portland OR US