18375084. INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING (INTEL CORPORATION)
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
Organization Name
Inventor(s)
Paul Packan of Hillsboro OR US
Conor P. Puls of Portland OR US
Chiao-Ti Huang of Portland OR US
Ting-Hsiang Hung of Beaverton OR US
Chia-Ching Lin of Portland OR US
Yang Zhang of Rio Rancho NM US
Chung-Hsun Lin of Portland OR US
Anand S. Murthy of Portland OR US
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
This abstract first appeared for US patent application 18375084 titled 'INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
Original Abstract Submitted
Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.
- INTEL CORPORATION
- Tao Chu of Portland OR US
- Minwoo Jang of Portland OR US
- Yanbin Luo of Portland OR US
- Paul Packan of Hillsboro OR US
- Conor P. Puls of Portland OR US
- Guowei Xu of Portland OR US
- Chiao-Ti Huang of Portland OR US
- Robin Chao of Portland OR US
- Feng Zhang of Hillsboro OR US
- Ting-Hsiang Hung of Beaverton OR US
- Chia-Ching Lin of Portland OR US
- Yang Zhang of Rio Rancho NM US
- Chung-Hsun Lin of Portland OR US
- Anand S. Murthy of Portland OR US
- H01L23/48
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H01L23/481
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