Intel corporation (20250098260). INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
Organization Name
Inventor(s)
Chiao-Ti Huang of Portland OR US
Chung-Hsun Lin of Portland OR US
Oleg Golonzka of Beaverton OR US
Yang Zhang of Rio Rancho NM US
Ting-Hsiang Hung of Beaverton OR US
Chia-Ching Lin of Portland OR US
Anand S. Murthy of Portland OR US
INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
This abstract first appeared for US patent application 20250098260 titled 'INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
Original Abstract Submitted
integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. for example, an integrated circuit structure includes a stack of horizontal nanowires. a gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. an internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. an external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.
- Intel corporation
- Guowei Xu of Portland OR US
- Feng Zhang of Hillboro OR US
- Chiao-Ti Huang of Portland OR US
- Robin Chao of Portland OR US
- Tao Chu of Portland OR US
- Chung-Hsun Lin of Portland OR US
- Oleg Golonzka of Beaverton OR US
- Yang Zhang of Rio Rancho NM US
- Ting-Hsiang Hung of Beaverton OR US
- Chia-Ching Lin of Portland OR US
- Anand S. Murthy of Portland OR US
- H01L29/66
- H01L29/06
- H01L29/08
- H01L29/423
- H01L29/49
- H01L29/775
- CPC H10D64/021
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