Intel Corporation patent applications published on November 30th, 2023

Summary of the patent applications from Intel Corporation on November 30th, 2023

Intel Corporation has recently filed several patents related to various aspects of technology. These patents cover areas such as layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects, electronic device display interfaces for camera control, network interface devices with direct memory access (DMA) circuitry, secure connections over Remote Direct Memory Access (RDMA), software-based management of the physical layer (PHY) of a link, adapting secure sounding signals in communication devices, implementing high-speed Ethernet links using a hybrid PHY, gate-all-around integrated circuit structures with tightly spaced nanowires, and thin film transistors with double gates.

Notable applications of these patents include:

• Layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects, including inter-cell mobility, split architectures, dynamic cell group changes, activation, and deactivation.
• Electronic device display interfaces for controlling a camera and reviewing captured images, providing a simplified and user-friendly interface.
• Network interface devices with direct memory access (DMA) circuitry for processing packets and determining Extended Sequence Number (ESN) values.
• Secure connections over Remote Direct Memory Access (RDMA) with two network interface devices, acting as endpoints for Transport Layer Security (TLS) over RDMA connections.
• Software-based application for managing the physical layer (PHY) of a link using an application programming interface (API) to configure the physical layer through firmware.
• Adapting secure sounding signals in communication devices based on negotiated bandwidth for secure communication.
• Implementing high-speed Ethernet links using a hybrid PHY with non-interleaved or interleaved RS-FEC sublayers, determined during link training.
• Gate-all-around integrated circuit structures with tightly spaced nanowires and methods for fabricating them.
• Thin film transistors with double gates for improved control and performance.

In summary, Intel Corporation has filed patents covering a wide range of technological advancements, including mobility aspects, camera control interfaces, network interface devices, secure connections, software-based management of the physical layer, adaptive sounding signals, high-speed Ethernet links, integrated circuit structures, and thin film transistors. These patents demonstrate Intel's commitment to innovation and advancing technology in various fields.

Patent applications for Intel Corporation on November 30th, 2023

SOCKETED MEMORY ARCHITECTURE PACKAGE AND METHOD (17825558)

Main Inventor

Siva Prasad Jangili Ganga

SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS (18449651)

Main Inventor

Raanan Sade

BOOT PROCESS FOR EARLY DISPLAY INITIALIZATION AND VISUALIZATION (18361128)

Main Inventor

Subrata Banik

SYSTEMS AND METHODS FOR IMPLEMENTING AN INTELLIGENT APPLICATION PROGRAM INTERFACE FOR AN INTELLIGENT OPTIMIZATION PLATFORM (18326467)

Main Inventor

Alexandra Johnson

POWER ERROR MONITORING AND REPORTING WITHIN A SYSTEM ON CHIP FOR FUNCTIONAL SAFETY (18302999)

Main Inventor

Prashant D. Chaudhari

ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER UPDATE MODE (18232765)

Main Inventor

Saravanan SETHURAMAN

USB TYPE-C SUBSYSTEM (17826933)

Main Inventor

Udaya Natarajan

MULTI-PORT MEMORY LINK EXPANDER TO SHARE DATA AMONG HOSTS (18250325)

Main Inventor

Zhuangzhi Li

AI-BASED COMPONENT PLACEMENT TECHNOLOGY FOR PCB CIRCUITS (18326772)

Main Inventor

Jianfang Zhu

MISUSE INDEX FOR EXPLAINABLE ARTIFICIAL INTELLIGENCE IN COMPUTING ENVIRONMENTS (18323843)

Main Inventor

GLEN J. ANDERSON

NEURAL NETWORK TRAINING AND INFERENCE WITH HIERARCHICAL ADJACENCY MATRIX (18325348)

Main Inventor

Emmanouil Ioannis Farsarakis

APPARATUS AND METHOD FOR SCALABLE QUBIT ADDRESSING (18231917)

Main Inventor

Xiang ZOU

LOSSY COMPRESSION TECHNOLOGY FOR SMALL IMAGE TILES (17824372)

Main Inventor

Sreenivas Kothandaraman

INCREMENTAL 2D-TO-3D POSE LIFTING FOR FAST AND ACCURATE HUMAN POSE ESTIMATION (18031564)

Main Inventor

Anbang YAO

METHOD AND APPARATUS FOR ENCODING BASED ON IMPORTANCE VALUES (18305175)

Main Inventor

Yejun Guo

FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING (18305511)

Main Inventor

Prasoonkumar Surti

GLARE AND OCCLUDED VIEW COMPENSATION FOR AUTOMOTIVE AND OTHER APPLICATIONS (18322665)

Main Inventor

Arthur J. Runyan

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION (18213231)

Main Inventor

Bill NALE

VIA STRUCTURE FOR EMBEDDED COMPONENT AND METHOD FOR MAKING SAME (17752941)

Main Inventor

Kristof Darmawikarta

Brief explanation

The patent application describes a via structure for an embedded component and a method for making it.

• The via structure consists of a conductive pillar attached perpendicularly to a surface of a build-up dielectric layer.
• The surface and the pillar are covered by a film layer that retains a specific profile.
• A dielectric layer is located on top of the film layer, with a planar upper surface.
• The top of the pillar is exposed at the upper surface of the dielectric layer.
• The film layer acts as a barrier to cracking and is chosen to be harder than the dielectric layer material.

Abstract

A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface. The film layer can act as a barrier to cracking because it is selected to have a higher hardness than the material making up the dielectric layer

INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING INTEGRATED CIRCUIT DEVICES THEREIN (17825340)

Main Inventor

Kai-Chiang Wu

Brief explanation

The abstract describes an integrated circuit assembly that includes a bridge connecting two integrated circuit devices in different levels of the assembly.

• The integrated circuit assembly has a bridge incorporated into one level structure.
• The bridge electrically interconnects at least two integrated circuit devices in another level structure.
• The assembly includes a first level structure with a first and second integrated circuit device.
• A second level structure is attached to the first integrated circuit device and the bridge forms an electrical attachment between the first and second integrated circuit devices.

Abstract

An integrated circuit assembly may be formed with a bridge incorporated into at least one level structure of the integrated circuit assembly, which electrically interconnects at least two integrated circuit devices in another level structure of the integrated circuit assembly. In one example, the integrated circuit assembly may include a first level structure that comprises at least a first integrated circuit device and a second integrated circuit device, and a second level structure comprising at least one integrated circuit device electrically attached to the first integrated circuit device of the first level structure and the bridge forming an electrical attachment between the first integrated circuit device of the first level structure and the second integrated circuit device of the first level structure.

INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING RETICLE BOUNDARY / DICING STREETS OF MONOLITHIC STRUCTURES THEREIN (17825350)

Main Inventor

Debendra Mallik

Brief explanation

The abstract describes an integrated circuit assembly that consists of two levels of structures.

• The first level structure includes a monolithic substrate with two reticle zones, each containing integrated circuitry.
• The second level structure consists of at least one integrated circuit device that is electrically attached to the integrated circuitry in the first reticle zone of the first level structure.
• A bridge is used to electrically connect the integrated circuitry in the first reticle zone of the first level structure with the integrated circuitry in the second reticle zone of the first level structure.

Abstract

An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION (18232670)

Main Inventor

Joseph STEIGERWALD

Brief explanation

- The patent application describes a new structure for a wrap-around source/drain trench contact in a semiconductor device.

- The structure includes multiple semiconductor fins extending from a substrate, with a channel region between each pair of source/drain regions. - An epitaxial semiconductor layer covers the top and sidewall surfaces of each fin, creating narrow gaps between adjacent fins. - Two source/drain trench contacts are connected to the epitaxial semiconductor layers. - The source/drain trench contacts consist of a conformal metal layer and a fill metal. - The conformal metal layer conforms to the epitaxial semiconductor layers. - The fill metal includes a plug and a barrier layer. - The plug fills a contact trench above the fins and the conformal metal layer. - The barrier layer lines the plug to prevent interdiffusion of materials between the conformal metal layer and the plug.

Abstract

A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

THIN FILM TRANSISTORS HAVING DOUBLE GATES (18227233)

Main Inventor

Abhishek A. SHARMA

Brief explanation

The patent application describes thin film transistors with double gates.

• Integrated circuit structure with insulator layer, first gate stack, and polycrystalline channel material layer.
• Second gate stack is placed on a portion of the polycrystalline channel material layer.
• First conductive contact is adjacent to one side of the second gate stack.
• Second conductive contact is adjacent to the other side of the second gate stack.
• The invention allows for improved control and performance of the thin film transistors.

Abstract

Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING (18228139)

Main Inventor

Glenn GLASS

Brief explanation

The patent application describes gate-all-around integrated circuit structures with tightly spaced nanowires and methods for fabricating them.

• The integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires.
• The vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers.
• A gate stack surrounds the vertical arrangement of horizontal silicon nanowires.
• A first source or drain structure is located at one end of the vertical arrangement of nanowires.
• A second epitaxial source or drain structure is located at the other end of the vertical arrangement of nanowires.

Abstract

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

ANTENNA SWITCHING FOR IMPROVED IN-DEVICE CO-EXISTENCE PERFORMANCE (18049651)

Main Inventor

Santhosh AP

Brief explanation

The abstract describes a mobile communication device that has a processor capable of performing certain functions.

• The device can retrieve a first isolation metric from a lookup table that relates to the connection between an antenna and a first additional antenna.
• It can also retrieve a second isolation metric from a lookup table that relates to the connection between the antenna and a second additional antenna.
• The device is able to determine that the second isolation metric is greater than the first isolation metric.
• Based on this determination, the device can switch the transmission of signals from the first additional antenna to the second additional antenna.

Abstract

A mobile communication device including a processor configured to: retrieve a first isolation metric from a lookup table between an antenna and a first further antenna; retrieve a second isolation metric from a lookup table between the antenna and the second further antenna; determine that the second isolation metric is greater than the first isolation metric; and switch transmitting the signal from the first further antenna to the second further antenna.

HYBRID PHY WITH INTERLEAVED AND NON-INTERLEAVED RS-FEC AND FEC MODE DETERMINATION DURING ADAPTIVE LINK TRAINING PROTOCOL (18199697)

Main Inventor

Kent Lusted

Brief explanation

- The patent application describes an apparatus and methods for implementing high-speed Ethernet links using a hybrid PHY (Physical layer) that can be configured to use either a non-interleaved RS-FEC (Reed Solomon Forward Error Correction) sublayer or an interleaved RS-FEC sublayer.

- An adaptive link training protocol is used during link training to determine whether to use the non-interleaved or interleaved RS-FEC during link DATA mode. - Training frames are exchanged between link partners, including control and status fields, to request and confirm the desired FEC mode to be used during link DATA mode. - The hybrid PHY includes both interleaved RS-FEC and non-interleaved RS-FEC sublayers for transmitter and receiver operations. - During link training, a determination is made to assess whether the local receiver is likely to encounter decision feedback equalizer (DFE) burst errors. If so, the interleaved FEC mode is selected; otherwise, the non-interleaved FEC mode is selected or remains the default FEC mode. - The apparatus and methods described in the patent application can be implemented for 100 GB ASE-CR1 and 100 GB ASE-KR1 Ethernet links and interfaces.

Abstract

Apparatus and methods for implementing high-speed Ethernet links using a hybrid PHY (Physical layer) selectively configurable to employ a non-interleaved RS-FEC (Reed Solomon Forward Error Correction) sublayer or an interleaved RS-FEC sublayer. An adaptive link training protocol is used during link training to determine whether to employ the non-interleaved or interleaved RS-FEC during link DATA mode. Training frames are exchanged between link partners including control and status fields used to respectfully request a non-interleaved or interleaved FEC mode and confirm the requested FEC mode is to be used during link DATA mode. The hybrid PHY includes interleaved RS-FEC and non-interleaved RS-FEC sublayers for transmitter and receiver operations. During link training, a determination is made to whether a local receiver is likely to see decision feedback equalizer (DFE) burst errors. If so, the interleaved FEC mode is selected; otherwise the non-interleaved FEC mode is selected or is the default FEC mode. The apparatus and methods may be implemented for 100 GB ASE-CR1 and 100 GB ASE-KR1 Ethernet links and interfaces.

ADAPTATION OF SECURE SOUNDING SIGNAL TO BANDWIDTH VARIATION (18190906)

Main Inventor

Feng JIANG

Brief explanation

- The patent application describes a system for adapting a secure sounding signal in communication devices.

- The system includes a device that determines the negotiated bandwidth for communication with another device. - Based on the negotiated bandwidth, the device generates a first bit stream using a specific number of bits. - The device also generates a second bit stream to generate a random phase. - Using a combination of the first and second bit streams, the device determines a secure long training field (LTF). - The device then sends a frame to the other device, which includes the secure LTF. - The innovation allows for secure communication by adapting the sounding signal based on the negotiated bandwidth.

Abstract

This disclosure describes systems, methods, and devices related to adaptation of secure sounding signal. A device may determine a negotiated bandwidth to be used when communicating with a first station device. The device may determine a first bit stream used to generate a cyclic shift diversity (CSD) value based on the negotiated bandwidth, wherein a first number of bits is used for the first bit stream when a first negotiated bandwidth is used, and wherein a second number of bits is used for the first bit stream when a second negotiated bandwidth is used. The device may determine a second bit stream used to generate a random phase. The device may determine a secure a long training field (LTF) based on a combination of the first bit stream and the second bit stream. The device may cause to send a frame to the first station device, wherein the frame comprises the secure LTF.

SOFTWARE-BASED PHYSICAL LAYER CONFIGURATION (18323812)

Main Inventor

Nishant S. Shah

Brief explanation

- The patent application describes a software-based application that manages the physical layer (PHY) of a link.

- The application uses an application programming interface (API) to send commands to the firmware of a media access controller or internal PHY hardware. - These commands are used to configure the physical layer of the link through the firmware. - The API abstracts the functions of the controller and/or PHY hardware, making it easier to configure the physical layer of the link. - The innovation allows for more efficient and streamlined management of the physical layer in a software-based manner.

Abstract

A software-based physical layer (PHY) management application is to configure a physical layer of a link through calls to an application programming interface (API) to send commands to firmware of a media access controller or internal PHY hardware of a platform. The commands to the firmware are to direct configuration of the physical layer of a link through the firmware, where the API abstracts functions of the controller and/or PHY hardware used to configure the physical layer of the link.

IN-NETWORK COMPUTE OPERATIONS UTILIZING ENCRYPTED COMMUNICATIONS (18230588)

Main Inventor

Helia A. NAEIMI

Brief explanation

The patent application describes an interface and circuitry that can establish secure connections over Remote Direct Memory Access (RDMA) with two network interface devices.

• The circuitry acts as an endpoint for a Transport Layer Security (TLS) over RDMA connection with the first network interface device.
• The circuitry also acts as an endpoint for a TLS over RDMA connection with the second network interface device.
• It provides a transport layer endpoint for the packets received from the first network interface device.
• It also provides a transport layer endpoint for the packets received from the second network interface device.

Abstract

Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a Transport Layer Security (TLS) over Remote Direct Memory Access (RDMA) connection with a first network interface device, provide an endpoint for a TLS over RDMA connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a transport layer endpoint for the packets received from the second network interface device.

ENCODING OF AN IMPLICIT PACKET SEQUENCE NUMBER IN A PACKET (18231726)

Main Inventor

Philip GLYNN

Brief explanation

The patent application describes a network interface device with direct memory access (DMA) circuitry, a network interface, a host interface, and circuitry.

• The circuitry processes packets received by the network interface.
• In a first configuration, the circuitry determines an Extended Sequence Number (ESN) value based on the content of the packet without using ESN prediction.
• In a second configuration, the circuitry determines ESN using prediction.

Abstract

Examples described herein relate to a network interface device. In some examples, the network interface device includes direct memory access (DMA) circuitry, a network interface, a host interface, and circuitry. The circuitry can be configured to process a packet received by the network interface; for a first configuration, determine an Extended Sequence Number (ESN) value based on content of the packet without performance of ESN prediction; and for a second configuration, determine ESN using prediction.

USER INTERFACES FOR ELECTRONIC DEVICES (18189789)

Main Inventor

Peter W. Winer

Brief explanation

- The patent application describes electronic device display interface embodiments for controlling a camera and reviewing captured images.

- The device includes a display for viewing images to be captured and controlling camera operation. - The display interface includes an image capture button and two or more smaller image mode buttons adjacent to it. - The image capture button is used to capture images, while the smaller image mode buttons provide options for different image modes. - The invention aims to provide a simplified and user-friendly interface for camera control and image review on electronic devices.

Abstract

Disclosed herein are electronic device display interface embodiments for controlling a camera and for reviewing images captured in the device from the camera. For example, in some embodiments, a device is provided with a display for viewing images to be captured by the camera and to provide a display interface for controlling camera operation, wherein the display interface, when in an image capture mode, is to provide an image capture button with two or more smaller image mode buttons disposed adjacent to the image capture button.

MOBILITY FEATURES FOR NEXT GENERATION CELLULAR NETWORKS (18352810)

Main Inventor

Yi Guo

Brief explanation

- The patent application is related to layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects.

- It covers various aspects of LTM, including inter-cell mobility, split architectures, dynamic cell group changes, activation, and deactivation. - It also includes conditional primary SCG cell addition or change (CPAC) aspects, early timing advance acquisition for LTM, and radio link monitoring (RLM) handling for LTM. - The patent application also addresses LTM-related security mechanisms and conditional handover (CHO)/CPAC aspects related to secondary cell group (SCG) configurations and radio resource control (re)configuration. - It may also cover reference configuration aspects. - The patent application may describe additional or alternative aspects related to LTM.

Abstract

The present disclosure is related to layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects, including LTM inter-cell mobility, LTM in split architectures; dynamic cell group changes, activation, and deactivation, conditional primary SCG cell addition or change (CPAC) aspects; early timing advance acquisition for LTM; radio link monitoring (RLM) handling for LTM; LTM-related security mechanisms; conditional handover (CHO)/CPAC aspects related to secondary cell group (SCG) configurations and radio resource control (re)configuration; and reference configuration aspects. Additional or alternative aspects may be described and/or claimed.