US Patent Application 18228139. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING simplified abstract

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GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING

Organization Name

Intel Corporation

Inventor(s)

Glenn Glass of Portland OR (US)

Anand Murthy of Portland OR (US)

Biswajeet Guha of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Susmita Ghose of Hillsboro OR (US)

Zachary Geiger of Hillsboro OR (US)

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18228139 titled 'GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING

Simplified Explanation

The patent application describes gate-all-around integrated circuit structures with tightly spaced nanowires and methods for fabricating them.

  • The integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires.
  • The vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers.
  • A gate stack surrounds the vertical arrangement of horizontal silicon nanowires.
  • A first source or drain structure is located at one end of the vertical arrangement of nanowires.
  • A second epitaxial source or drain structure is located at the other end of the vertical arrangement of nanowires.


Original Abstract Submitted

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

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