Micron Technology, Inc. patent applications published on November 30th, 2023

Summary of the patent applications from Micron Technology, Inc. on November 30th, 2023

Micron Technology, Inc. has recently filed several patents related to microelectronic devices, memory arrays, and key management systems. These patents aim to improve memory cell functionality, organization, and manufacturing processes.

Summary: Micron Technology, Inc. has filed patents for microelectronic devices consisting of source and stack structures, with slits and memory cell pillars extending through them. They have also filed patents for memory arrays formed using stacks of insulative and conductive tiers, with channel-material strings and conductive vias. Another patent describes memory arrays with memory blocks organized into vertical stacks of insulative and conductive tiers, including different compositions of insulative tiers. Additionally, Micron has filed patents for memory arrays formed using alternating tiers of different materials, with sacrificial plugs and upper channel-material strings. They have also filed patents for electronic devices with stack structures made of dielectric and conductive materials, and for microelectronic devices with vertically stacked memory cells and control logic devices. Furthermore, Micron has filed patents for interfaces between memory modules and circuit boards, and for securely updating semiconductor devices using a key management system. Lastly, they have filed a patent for manufacturing textured optoelectronic devices using conductive transparent texturing materials.

Bullet Points:

• Micron Technology, Inc. has filed patents for microelectronic devices, memory arrays, and key management systems.
• The patents aim to improve memory cell functionality, organization, and manufacturing processes.
• They include devices with source and stack structures, slits, and memory cell pillars.
• Memory arrays are formed using insulative and conductive tiers, with channel-material strings and conductive vias.
• Different compositions of insulative tiers and sacrificial plugs are also utilized.
• Electronic devices have stack structures made of dielectric and conductive materials.
• Interfaces between memory modules and circuit boards are also covered.
• Securely updating semiconductor devices is achieved through a key management system.
• Textured optoelectronic devices are manufactured using conductive transparent texturing materials.

Notable Applications:

• Microelectronic devices with improved memory cell functionality and organization.
• Memory arrays formed using insulative and conductive tiers, with channel-material strings and conductive vias.
• Memory arrays with memory blocks organized into vertical stacks of insulative and conductive tiers.
• Electronic devices with stack structures made of dielectric and conductive materials.
• Interfaces between memory modules and circuit boards.
• Securely updating semiconductor devices using a key management system.
• Manufacturing textured optoelectronic devices using conductive transparent texturing materials.

Patent applications for Micron Technology, Inc. on November 30th, 2023

VOLTAGE TRACKING CIRCUIT (17824479)

Main Inventor

Leon Zlotnik

Brief explanation

The abstract describes a voltage tracking circuit that includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. 

• The voltage tracking circuit determines a first voltage based on the number of active delay line blocks and a second voltage based on information from the phase detection circuitry.
• The circuit then determines the measured value of a voltage provided by the voltage regulator based on the first and second voltages.
• The voltage tracking circuit helps regulate and track the voltage provided by the voltage regulator.
• The circuit uses delay line blocks and phase detection circuitry to accurately determine the voltage values.
• The controller plays a key role in determining the measured value of the voltage.
• This innovation can be used in various applications where precise voltage regulation is required.

Abstract

A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.

LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT (17824749)

Main Inventor

Manjunath Chandrashekaraiah

Brief explanation

The abstract describes a method, apparatus, and system for managing the health of a memory device.

• The device health manager identifies a memory device with a service life.
• The device health manager receives multiple requests to perform computing operations.
• The device health manager uses a machine learning model to predict an adjustment of the memory device's service life based on health data.
• The device health manager generates a notification that includes the adjustment of the service life.

Abstract

Exemplary methods, apparatuses, and systems including a device health manager for managing health of a memory device. The device health manager identifies a memory device having a service life. The device health manager receives multiple requests to perform one or more computing operations. The device health manager predicts, using a machine learning model, an adjustment of the service life of the memory device using the health data. The device health manager generates a notification including the adjustment of the service life.

CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE (17804153)

Main Inventor

Jeremy BINFET

Brief explanation

- The patent application is for a memory device that can receive a command to access a specific block of memory.

- The memory device can also receive a cryptographic signature associated with the command. - Based on the command and the cryptographic signature, the memory device can enable or disable access to the block of memory. - The memory device has the capability to restrict access to each individual block of memory separately.

Abstract

A memory device may be configured to receive a command to access a block of memory that is one of multiple blocks of memory included in the memory device. The memory device may be configured to receive a cryptographic signature associated with the command. The memory device may be configured to enable or disable access to the block of memory based on the command and based on the cryptographic signature. The memory device may be capable of separately restricting access to each individual block of the multiple blocks.

TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS (17752354)

Main Inventor

Roberto Izzi

Brief explanation

This patent application describes methods, systems, and devices for detecting shutdown patterns in a memory device. 

• A memory device receives a set of commands from a host device.
• The memory device analyzes the pattern of the received commands to determine if they are associated with a shutdown procedure.
• If the commands are associated with a shutdown procedure, the memory device initiates one or more operations related to the shutdown.
• The memory device can also receive a shutdown command specifically for the shutdown procedure.
• The determination of whether the commands are part of the shutdown procedure can be based on the quantity or types of commands, predefined thresholds, or a combination of factors.

Abstract

Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION (17824725)

Main Inventor

Donghua Zhou

Brief explanation

The patent application describes a method for configuring non-volatile memory blocks to improve memory operation performance. Here are the key points:

• The method selectively configures a subset of non-volatile memory blocks to operate in a single-level mode.
• The first subset of memory blocks is then collectively configured to function as a pseudo single-level cache.
• Data associated with memory operation performance is written to the first subset of memory blocks.
• The data is later migrated from the first subset of memory blocks to a second subset of memory blocks.

Abstract

A method includes selectively configuring a first subset of non-volatile memory blocks to operate in a single-level mode, configuring the first subset of non-volatile memory blocks to collectively operate as a pseudo single-level cache, writing data associated with performance of a memory operation to the first subset of non-volatile memory blocks, and migrating the data from the first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks.

CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES (17806888)

Main Inventor

Alyssa SCARBROUGH

Brief explanation

The patent application describes a device that can receive sensor data from a vehicle's sensor.

• The device can determine if an event that could damage the vehicle has occurred or is likely to occur based on the sensor data exceeding a certain threshold.
• The threshold is determined by the vehicle's on-off status and the type of sensor being used.
• If the event is detected, the device can activate the vehicle's camera to capture video of the scene.
• The device can then send an indication of the event and the captured video data to a server.

Abstract

In some implementations, a device may receive, from a sensor of a vehicle, sensor data. The device may detect whether an event causing damage to the vehicle has occurred or is expected to occur based on the sensor data being greater than a threshold, wherein the threshold is based on an on-off status of the vehicle and a sensor type. The device may activate, based on whether the event has occurred or is expected to occur, a camera of the vehicle to capture video data of a scene associated with the vehicle. The device may transmit, to a server, an indication that indicates the event and the video data.

Data Recorders of Autonomous Vehicles (18326972)

Main Inventor

Gil Golov

Brief explanation

- This patent application describes a system for collecting sensor data in an autonomous vehicle.

- The vehicle's sensors generate a continuous stream of data, which is stored in two separate cyclic buffers. - The first cyclic buffer stores a smaller segment of the data, while the second cyclic buffer stores a larger segment. - The vehicle's advanced driver assistance system can detect or predict accidents and faults in object detection. - When an accident is detected, a segment of the sensor data stream is copied from the first cyclic buffer to a non-volatile memory slot. - The non-volatile memory has multiple slots, and the copied segment is placed in a slot selected in a round-robin manner. - When a fault in object detection is detected, a segment of the sensor data stream is copied from the second cyclic buffer to a different area of the non-volatile memory. - This different area is outside of the slots reserved for the first cyclic buffer.

Abstract

Systems, methods and apparatus to collect sensor data generated in an autonomous vehicle. Sensors of the vehicle generate a sensor data stream that is buffered, in parallel and in a cyclic way, in a first cyclic buffer and a larger second cyclic buffer respectively. An advanced driver assistance system of the vehicle generates an accident signal when detecting or predicting an accident and provides a training signal when detecting a fault in object detection, recognition, identification or classification. The accident signal causes a sensor data stream segment to be copied from the first cyclic buffer into a slot of a non-volatile memory, selected from a plurality of slots in a round robin way. The training signal causes a sensor data stream segment to be copied from the second cyclic buffer into an area of the non-volatile memory outside of the slots reserved for the first cyclic buffer.

BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE (18326984)

Main Inventor

Gil Golov

Brief explanation

The abstract describes an improved black box data recorder for autonomous driving vehicles (AVD).

• The black box has two cyclic buffers to record vehicle sensor data.
• The first cyclic buffer records raw sensor data on a volatile memory.
• The second cyclic buffer records the same sensor data as compressed data on a non-volatile memory.
• In the event of a collision or near collision, the buffers are flushed into a non-volatile storage for retrieval.
• The raw sensor data can be accessed from the non-volatile storage as long as there is no power interruption.
• If a power interruption occurs, the raw sensor data in the volatile memory will be lost, but the compressed data in the non-volatile memory will still be accessible.

Abstract

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING (18202584)

Main Inventor

Peter Mayer

Brief explanation

This patent application describes methods, systems, and devices for calibrating the drive strength of a driver in a multi-level signaling system. Here are the key points:

• The driver in a transmitting device is initially set to a certain drive strength and is used to drive an output pin towards an intermediate voltage level in a multi-level modulation scheme.
• The output pin is connected to a receiving device through a channel.
• The receiving device generates a feedback signal that indicates the relationship between the resulting voltage in the channel and the value for the intermediate voltage level.
• The transmitting device receives this feedback signal.
• Based on the feedback signal, the transmitting device determines and adjusts the drive strength of the driver for the intermediate voltage level.
• The driver can be calibrated independently for each intermediate voltage level in the multi-level modulation scheme.
• The driver can also be calibrated specifically for the associated channel.

Abstract

Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

APPARATUSES AND METHODS FOR COMMAND DECODING (17752573)

Main Inventor

YUTAKA UEMURA

Brief explanation

The patent application describes a command decoder with multiple command paths.

• Command signals from one command path can be sent to another command path through a node located between two latches.
• The command decoder includes separate flip-flops for different command modes.
• These separate flip-flops may be tristate flip-flops.
• Instead of a multiplexer, the command decoder may use alternate logic circuits.

Abstract

In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.

APPARATUSES AND METHODS FOR COMMAND DECODING (17752605)

Main Inventor

YUTAKA UEMURA

Brief explanation

The patent application describes a command decoder with multiple command paths.

• The command signals from one command path can be sent to another command path through a node located between two latches.
• The command decoder includes separate flip-flops for different command modes.
• These separate flip-flops can be tristate flip-flops.
• Instead of a multiplexer, the command decoder can use alternate logic circuits.

Abstract

In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS (18232949)

Main Inventor

Eric N. Lee

Brief explanation

The patent application describes a memory device that consists of an array of memory cells, access lines, and control logic.

• The memory cells are arranged in strings, with each string containing multiple series-connected memory cells.
• Each access line is connected to the control gate of a memory cell in each string.
• The control logic is designed to perform various read operations on the memory cells.
• The memory cells can be opened for multiple read operations.
• The first page data is read from the memory cells connected to a selected access line.
• The second page data is also read from the same memory cells.
• After reading the first and second page data, the memory cells are closed.

Abstract

Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES (17829046)

Main Inventor

Tong Liu

Brief explanation

The patent application describes a memory device with a plate line and a pair of ferroelectric layers that act as memory cells.

• The ferroelectric layers are connected to opposite sides of the plate line.
• Each ferroelectric layer is also connected to a digit line.
• A sense amplifier is connected to the digit lines and amplifies the voltages received from the memory cells.
• The sense amplifier includes a threshold voltage compensated latch.
• The latch is made up of multiple p-channel transistors.
• The latch compensates for variations in threshold voltages due to process, voltage, or temperature differences.

Abstract

Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE (18202659)

Main Inventor

Perry V. Lea

Brief explanation

The patent application describes apparatuses and methods for a memory device to perform operations while in a self-refresh state.

• The memory device includes an array of memory cells and a controller.
• The controller is responsible for directing compute operations on data stored in the memory array.
• These operations can be performed even when the memory array is in a self-refresh state.

Abstract

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION (17825600)

Main Inventor

YOSHIYA KOMATSU

Brief explanation

The patent application describes apparatuses, systems, and methods for mitigating bias temperature instability (BTI).

• The invention includes a BTI oscillator that generates a periodic BTI signal.
• A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal.
• A clock gating circuit passes the clock signal to a clock path only when the periodic BTI signal is active.
• In the absence of an external clock, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.
• The invention aims to address the issue of BTI in electronic devices by providing a mechanism to mitigate its effects.
• By synchronizing the BTI pulse signal with the clock signal and selectively passing the clock signal, the invention helps prevent BTI-induced errors in memory operations.
• The use of a BTI oscillator and logic circuit allows for efficient and accurate BTI mitigation.
• The invention can be implemented in various electronic devices, such as computers, smartphones, and IoT devices.

Abstract

Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.

APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT (17827582)

Main Inventor

Ryo Fujimaki

Brief explanation

- The patent application describes apparatuses and methods for arranging read data for output.

- The apparatus includes a clock circuit, a data output circuit, and a control circuit. - The clock circuit generates multiphase clock signals with different phases based on a clock signal. - The data output circuit receives multiple read data bits and outputs them serially in sync with the multiphase clock signals. - The control circuit determines the correspondences between the read data bits and the multiphase clock signals based on information about which clock signal captures the read command.

• The invention aims to improve the arrangement of read data for output.
• It utilizes multiphase clock signals to synchronize the output of read data bits.
• The use of different phases in the clock signals helps in organizing the read data bits.
• The control circuit determines the appropriate correspondence between the read data bits and the clock signals.
• This invention can enhance the efficiency and accuracy of data output in various applications.

Abstract

Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.

METHODS OF CONFIGURING A MEMORY (18232386)

Main Inventor

Pin-Chou Chiang

Brief explanation

The patent application describes methods for configuring a memory.

• The methods involve determining the read window budget for programming the memory based on the programming step voltage and the age of the memory cells.
• The programming step voltage is determined for each age of the memory cells to achieve the desired read window budget.
• The determined programming step voltage for each age of the memory cells is stored in the memory as data.
• This configuration method allows for efficient programming of the memory cells based on their age, ensuring optimal performance.

Abstract

Methods of configuring a memory might include characterizing a read window budget for a programming operation of the memory as a function of a programming step voltage for a plurality of memory cell ages, determining a respective programming step voltage for each memory cell age of the plurality of memory cell ages in response to a desired read window budget, and storing data to the memory indicative of the determined respective programming step voltage for each memory cell age of the plurality of memory cell ages.

WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE (17752785)

Main Inventor

Mattia Robustelli

Brief explanation

The patent application is related to memory devices and describes a memory array with first and second tiles, each containing memory cells. 

• The memory cells in the tiles are selected using wordlines.
• A controller programs the selected memory cells by applying a first voltage to a first wordline and a second voltage to a second wordline.
• The first and second voltages are applied in a counter-phase manner.
• Charge sharing between the first and second wordlines boosts the second voltages.

Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes a memory array. The memory array has first tiles and second tiles. Each of the tiles includes memory cells. Wordlines are configured to select the memory cells in the first and second tiles. A controller programs the selected memory cells by applying a first voltage to a first wordline, and a second voltage to a second wordline. The first and second voltages are applied in a counter-phase manner. The second voltages boosted by charge sharing between the first and second wordlines.

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17752207)

Main Inventor

Haoyu Li

Brief explanation

The patent application describes a memory array made up of strings of memory cells, with a conductor tier made of conductor material. The memory blocks are stacked vertically and consist of alternating insulative tiers and conductive tiers. The memory cells are connected by channel-material strings that pass through the insulative and conductive tiers. The lower conductive tier directly connects the channel material and the conductor material.

• Memory array with strings of memory cells and a conductor tier
• Memory blocks stacked vertically with insulative and conductive tiers
• Channel-material strings connect memory cells through the tiers
• Lower conductive tier directly connects channel material and conductor material
• Lower conductive tier made up of upper and lower conductively-doped semiconductive material with intermediate material in between
• Intermediate material has different composition and can include carbon, nitrogen, oxygen, metal, and n-type doped material with boron
• Other embodiments and methods are also disclosed in the patent application.

Abstract

A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.

PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE (17825439)

Main Inventor

Zhongguang Xu

Brief explanation

The patent application describes a protocol for handling a closed block of memory in a processing device's memory sub-system.

• The block consists of multiple wordlines.
• The processing device sends a first programming command to the memory device to program adjacent wordlines of the block with first padding data.
• The processing device also sends a second programming command to concurrently program the remaining wordlines of the block to a threshold voltage.

Abstract

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM (17752590)

Main Inventor

Yu-Chung Lien

Brief explanation

The patent application describes a system that includes a memory device and a processing device.

• The system receives a programming command for a set of memory cells.
• The processing device determines a metric value that reflects the state of the memory cells.
• Based on the metric value, the processing device determines a delay for the programming operation.
• The processing device then performs the programming operation on the subset of memory cells.
• The programming operation includes a delay between the first pass and the second pass of the operation.

Abstract

A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

MEDIA MANAGEMENT (17824384)

Main Inventor

Donghua Zhou

Brief explanation

The patent application describes a method for managing memory cells in a device.

• The method involves determining the difference between two health characteristic values of memory cell blocks and comparing it to a health threshold.
• If the difference is greater than or equal to a predetermined threshold, a pseudo media management operation is performed on the memory cell blocks.
• After the operation, an updated health characteristic value is determined for the memory cell blocks.

Abstract

A method includes determining a gap between a difference in a first health characteristic value and a second health characteristic value of blocks of memory cells and a health threshold associated with the blocks of memory cells, determining the gap is greater than or equal to a gap threshold from the health threshold, performing a pseudo media management operation on the blocks of memory cells, and determining an updated first health characteristic value of the blocks of memory cells.

INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES (18109830)

Main Inventor

Eric J. Stave

Brief explanation

- The patent application is about interposers used for testing and characterizing memory devices, specifically those with decision feedback equalization circuitry.

- The interposer has two interfaces, one for connecting to the memory device and the other for connecting to one or more testers. - There is a channel circuit within the interposer that allows signals to be transmitted between the memory device and the testers. - The channel circuit can be configured using resistive elements to change a measurable value of the transmitted signal. - The purpose of this innovation is to provide a means for testing and characterizing memory devices more effectively and accurately.

Abstract

Interposers for use in testing and characterizing memory devices, such as memory devices including decision feedback equalization circuitry, are disclosed herein. In one embodiment, an apparatus includes an interposer having a first interface couplable to a memory device, a second interface couplable to one or more testers, and a channel circuit between the first interface and the second interface. The channel circuit is configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.

NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS (17827006)

Main Inventor

Kunal R. Parekh

Brief explanation

- This patent application is about semiconductor devices with nano through substrate vias (TSVs).

- The semiconductor device includes a semiconductor substrate with a trench filled with a dielectric material. - The TSV extends from the first surface to the second surface within the trench. - The TSV is made of a conductive material with a first portion and a second portion. - The first portion has a larger cross-sectional area at the second end compared to the first end. - The second portion has a larger cross-sectional area at the fourth end compared to the third end.

Abstract

Semiconductor devices having nano through substrate vias (TSVs), and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite the first surface. A trench is formed in the first surface and filled with a dielectric material and a TSV extends from the first surface to the second surface within the footprint of the trench. In some embodiments, the TSV includes a conductive material that includes a first portion and a second portion. The first portion includes a first end at the first surfacer and a second end with a larger cross-sectional area than the first end. Similarly, the second portion includes a third end coupled to the second end and a fourth end at the second surface with a larger cross-sectional area than the third end.

MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER (17826776)

Main Inventor

Shuangqiang Luo

Brief explanation

The patent application describes apparatuses and methods for forming memory cells and control gates.

• The apparatus includes tiers with memory cells and control gates, and conductive contacts that have different lengths between tiers.
• There is a contact structure adjacent to one of the conductive contacts.
• The contact structure has a conductive core portion and a dielectric liner portion.
• The dielectric liner portion consists of three different dielectric materials layered together.
• The purpose of the contact structure is to provide electrical connectivity while maintaining separation from the control gates.

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; conductive contacts contacting the control gates, the conductive contacts having different lengths extending in a direction from one tier to another tier among the tiers; and a contact structure adjacent one of the conductive contacts. The contact structure includes a conductive core portion extending through the tiers and separated from the control gates, and a dielectric liner portion adjacent the conductive core portion. The dielectric liner portion includes a first dielectric material, a second dielectric material adjacent the first dielectric material, and a third dielectric material adjacent the second dielectric material.

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804247)

Main Inventor

Fatma Arzum Simsek-Ege

Brief explanation

The patent application describes a microelectronic device that consists of two layers of microelectronic structures stacked on top of each other.

• The first layer includes a memory array region and a control logic device region that controls the memory cells in the memory array.
• The second layer also includes a memory array region and a control logic device region that controls the memory cells in the second memory array.
• The device can perform control operations on both memory arrays simultaneously.
• The patent also covers related memory devices, electronic systems, and methods.

Abstract

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804251)

Main Inventor

Fatma Arzum Simsek-Ege

Brief explanation

The patent application describes a microelectronic device that includes two layers of microelectronic structures.

• The first layer consists of a memory array region with memory cells.
• The second layer is positioned above the first layer and contains control logic devices responsible for controlling the memory cells.
• The second layer also includes first multi-capacitor structures that are placed between the control logic devices and their neighboring devices.
• These first multi-capacitor structures have the same number of routing tiers as the control logic devices or fewer.
• The purpose of the first multi-capacitor structures is to regulate and supply voltage to the control logic devices.

Abstract

A microelectronic device includes a first microelectronic device structure including a memory array region comprising memory cells and a second microelectronic device structure vertically overlying the first microelectronic device structure. The second microelectronic device structure includes control logic devices configured to effectuate at least a portion of control operations for the memory cells and first multi-capacitor structures within spaces between the control logic devices and horizontally neighboring at least one of the control logic devices. The first multi-capacitor structures span a same or fewer number of routing tiers as the control logic devices and are configured to regulate and supply voltage to one or more of the control logic devices.

RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING (17825695)

Main Inventor

Chong Leong Gan

Brief explanation

- This patent application is about radiation hard semiconductor devices and packaging.

- The semiconductor device assembly includes a substrate, a semiconductor die stack, and an ionizing radiation shield. - The ionizing radiation shield is made of silicon carbide (SiC). - The semiconductor die stack and the ionizing radiation shield are partially encapsulated by an encapsulant. - The purpose of this invention is to protect the semiconductor devices from ionizing radiation. - The use of silicon carbide as the material for the ionizing radiation shield enhances the radiation resistance of the semiconductor device assembly.

Abstract

Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS (17804530)

Main Inventor

Everett A. McTeer

Brief explanation

- The patent application describes a microelectronic device that consists of alternating conductive and insulative structures.

- The insulative structures have interfacial regions and a central region. - The interfacial regions are doped with carbon and/or boron. - The insulative structures have a lower concentration of carbon and/or boron compared to the interfacial regions. - The invention also includes other microelectronic devices, electronic systems, and methods.

Abstract

A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

TRANSISTOR WITH GATE ATTACHED FIELD PLATE (17752610)

Main Inventor

Michael A. Smith

Brief explanation

The patent application describes an apparatus that includes a substrate and a transistor on the substrate.

• The transistor has a gate between a source area and a drain area.
• The transistor also has routing lanes above the gate for automated routing programs to layout metal connections.
• A first field plate is placed above a LDD region of the source area, on the same level as the routing lanes.
• A second field plate is placed above a LDD region of the drain area, also on the same level as the routing lanes.
• The first and second field plates are electrically connected to the gate using separate paths that bypass the routing lanes.

Abstract

An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.

TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE (18359795)

Main Inventor

Lifang Xu

Brief explanation

- The patent application describes a method of manufacturing textured optoelectronic devices.

- The method involves applying a conductive transparent texturing material onto a substrate. - A transparent conductive material is then formed on top of the texturing material. - When the device is heated, the texturing material causes the conductive material to develop multiple raised areas called protuberances. - These protuberances enhance the spreading of current and extraction of light from the device. - The innovation aims to improve the performance of solid state optoelectronic devices.

Abstract

Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE (18448815)

Main Inventor

Lance W. Dover

Brief explanation

- The patent application is related to securely updating a semiconductor device and specifically focuses on a key management system.

- The disclosed method involves receiving a request for an activation code database from a remote computing device. - The request includes at least one parameter, which is used to retrieve at least one pair consisting of a unique ID (UID) and secret key. - An activation code is generated for the UID. - The activation code is then returned to the remote computing device.

Abstract

The disclosed embodiments are related to securely updating a semiconductor device and in particular to a key management system. In one embodiment, a method is disclosed comprising receiving a request for an activation code database from a remote computing device, the request including at least one parameter; retrieving at least one pair based on the at least one parameter, the pair including a unique ID (UID) and secret key; generating an activation code for the UID; and returning the activation code to the remote computing device.

INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS (17804789)

Main Inventor

Anthony D. Veches

Brief explanation

The patent application is about interfaces between memory modules and circuit boards.

• The patent focuses on interfaces that allow memory modules to be arranged parallel to the circuit board.
• It includes various embodiments of interfaces, memory modules, and circuit boards.
• The patent also covers associated devices and systems.

Abstract

This disclosure relates generally to interfaces between memory modules and circuit boards. More specifically, this disclosure relates to interfaces for coupling a memory module to a circuit board such that the memory module is arranged in a plane that is substantially parallel with a plane of the circuit board. Various embodiments disclosed herein include interfaces, memory modules including interfaces or portions of interfaces, and/or circuit boards including interfaces and/or portions of interfaces. Associated devices and systems are also disclosed.

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804234)

Main Inventor

Fatma Arzum Simsek-Ege

Brief explanation

The patent application describes a microelectronic device that consists of a vertical stack of memory cells. 

• The vertical stack includes a stack of access devices and capacitors that are positioned horizontally next to the access devices.
• There is a conductive pillar structure that connects to the access devices and an isolated conductive structure that connects to a multiplexer.
• The microelectronic device also includes a stack structure made up of conductive and insulative structures that are interleaved.
• Some of the conductive structures in the stack structure are connected to individual memory cells and serve as the gate for the access devices in the vertical stack.
• The patent application also mentions related electronic systems and methods.

Abstract

A microelectronic device comprises a vertical stack of memory cells. The vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, a conductive pillar structure in electrical communication with the vertical stack of access devices, and an isolated conductive structure in electrical communication with a multiplexer comprising a vertically uppermost access device of the vertical stack of access devices. The microelectronic device further comprises a stack structure comprising conductive structures interleaved with insulative structures, at least some of the conductive structures individually in electrical communication with a memory cell of the vertical stack of memory cells and comprising a gate of an access device of the vertical stack of access devices. Related electronic systems and methods are also described.

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804270)

Main Inventor

Fatma Arzum Simsek-Ege

Brief explanation

The patent application describes a microelectronic device that consists of two vertically stacked microelectronic device structures.

• The first microelectronic device structure has a memory array region and a control logic device region.
• The second microelectronic device structure also has a memory array region and a control logic device region.
• A third control logic device region is positioned above the second microelectronic device structure.
• The first control logic device region includes sense amplifier devices for the first memory array region.
• The second control logic device region includes additional sense amplifier devices and sub word line drivers for the second memory array region.
• The third control logic device region includes additional sub word line drivers for the second memory array region.
• The patent application also covers related microelectronic devices, electronic systems, and methods.

Abstract

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically neighboring the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region and the second microelectronic device structure comprises a second memory array region and a first control logic device region. A third control logic device region vertically overlies the second microelectronic device structure. The first control logic device region includes sense amplifier devices for the first memory array region. The second control logic device region includes additional sense amplifier devices and sub word line drivers for the second memory array region. The third control logic device region includes additional sub word line drivers for the second memory array region. Related microelectronic devices, electronic systems, and methods are also described.

ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING (17804752)

Main Inventor

Yifen Liu

Brief explanation

- The patent application describes an electronic device that includes a stack structure made up of alternating dielectric and conductive materials.

- The conductive materials in the stack have two regions, and there are pillars that extend vertically through the stack structure, located next to the second regions of the conductive materials. - The pillars have cell films that are made up of various materials, including a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material. - Segments of the high-k dielectric material, barrier oxide material, and storage node material are located next to the second regions of the conductive materials. - The length of these segments of high-k dielectric material and storage node material adjacent to the second regions is greater than the height of the first regions of the conductive materials.

Abstract

An electronic device includes a stack structure including vertically alternating dielectric materials and conductive materials, the conductive materials including first regions and second regions, and pillars extending vertically through the stack structure, the pillars adjacent to the second regions of the conductive materials. The pillars include cell films adjacent to the second regions, the cell films including a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material. Segments of each of the high-k dielectric material, the barrier oxide material, and the storage node material are adjacent to the second regions. A length of the segments of high-k dielectric material and a length of the segments of storage node material adjacent to the second regions are greater than a height of the first regions of the conductive materials. Related methods and systems are also disclosed.

Memory Circuitry And Method Used In Forming Memory Circuitry (17751978)

Main Inventor

Collin Howder

Brief explanation

The patent application describes a method for forming a memory array using a stack of alternating tiers of different materials.

• The stack includes lower channel-material strings that extend through the tiers.
• A sacrificial plug made of sacrificial material is placed above the lower channel-material strings.
• The sacrificial material is removed from the corner regions of the plug in a specific pattern.
• Insulator material is then formed in the spaces left by the removal of the sacrificial material.
• The remaining volume of the sacrificial plug is removed.
• Upper channel-material strings are formed below the insulator material and are connected to the lower channel-material strings.
• The patent also mentions other embodiments and structures.

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.

Memory Circuitry And Method Used In Forming Memory Circuitry (17869586)

Main Inventor

Jordan D. Greenlee

Brief explanation

The patent application describes a memory array with strings of memory cells that are organized into memory blocks. These memory blocks consist of vertical stacks of alternating insulative and conductive tiers. The memory cells are made up of channel-material strings that pass through these tiers. 

• The memory array includes laterally-spaced memory blocks with vertical stacks of insulative and conductive tiers.
• The memory cells are organized into strings that pass through these tiers.
• There is a second vertical stack alongside the first one, which consists of insulative tiers with different compositions.
• The different compositions of the insulative tiers include silicon nitride.
• One of the compositions is carbon-doped silicon nitride with a higher carbon content than the other compositions.
• The patent application also mentions other embodiments and methods related to this memory array.

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17879140)

Main Inventor

Adam Barton

Brief explanation

The patent application describes a method for forming a memory array using a stack of insulative and conductive tiers.

• The memory array includes channel-material strings of memory-cell strings that extend through the insulative and conductive tiers.
• Conductive vias are formed above the channel-material strings and are directly electrically coupled to them.
• Digitlines are formed above the conductive vias and are also directly electrically coupled to them.
• The digitlines are formed by depositing lower elemental-form tungsten directly on top of the conductive vias.
• The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WO (tungsten oxide) with a thickness of 0-30 Angstroms.
• Upper elemental-form tungsten is then physically vapor deposited directly on top of the WO.
• The patent application also mentions other embodiments and structures.

Abstract

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually directly electrically coupled to individual of the channel-material strings. Digitlines are formed above and are individually directly electrically coupled to a plurality of individual of the conductive vias there-below. The forming of the digitlines comprises forming lower elemental-form tungsten directly against tops of the individual conductive vias. The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WO, where “x” is greater than 0 and no more than 3.0. The WOhas a maximum thickness greater than 0 and no more than 30 Angstroms in a finished construction. Upper elemental-form tungsten is physical vapor deposited directly against the WO. Other embodiments, including structure, are disclosed.

METHODS OF FORMING MICROELECTRONIC DEVICES (18359792)

Main Inventor

Collin Howder

Brief explanation

- The patent application describes a microelectronic device that consists of a source structure and a stack structure.

- The stack structure is made up of alternating insulative and conductive structures arranged vertically. - Slits filled with a material extend through the stack structure and into the source structure, dividing the stack structure into multiple blocks. - Memory cell pillars also extend through the stack structure and into the source structure. - The memory cell pillars and filled slits terminate at the same depth within the source structure. - The innovation allows for improved memory cell functionality and organization within the microelectronic device.

Abstract

A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.