US Patent Application 17752590. ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM simplified abstract
Contents
ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM
Organization Name
Inventor(s)
Yu-Chung Lien of San Jose CA (US)
Zhenming Zhou of San Jose CA (US)
ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 17752590 titled 'ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM
Simplified Explanation
The patent application describes a system that includes a memory device and a processing device.
- The system receives a programming command for a set of memory cells.
- The processing device determines a metric value that reflects the state of the memory cells.
- Based on the metric value, the processing device determines a delay for the programming operation.
- The processing device then performs the programming operation on the subset of memory cells.
- The programming operation includes a delay between the first pass and the second pass of the operation.
Original Abstract Submitted
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.
