Category:Anand S. Murthy of Portland OR US
Anand S. Murthy
Anand S. Murthy from Portland OR US has applied for patents in technology areas such as G11C5/06, G11C11/4091, G11C11/419 with intel corporation.
Patents
Pages in category "Anand S. Murthy of Portland OR US"
The following 26 pages are in this category, out of 26 total.
1
- 18370287. INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS (Intel Corporation)
- 18372506. INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS (Intel Corporation)
- 18374600. TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER (INTEL CORPORATION)
- 18374607. MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL LAYOUT EFFECT TUNING (INTEL CORPORATION)
- 18375084. INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING (INTEL CORPORATION)
- 18467947. CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER (Intel Corporation)
- 18471382. STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE (Intel Corporation)
- 18471402. STACKED MEMORY LAYERS WITH UNIFORM ACCESS (Intel Corporation)
- 18473421. MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION (Intel Corporation)
- 18498318. INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS (Intel Corporation)
- 19004029. FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM (Intel Corporation)
2
I
- Intel corporation (20250008723). THREE-DIMENSIONAL FLOATING BODY MEMORY
- Intel corporation (20250022878). USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR ARRANGEMENTS
- Intel corporation (20250095693). CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
- Intel corporation (20250098260). INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
- Intel corporation (20250104760). STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Intel corporation (20250107107). STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Intel corporation (20250107108). MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Intel corporation (20250107175). INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Intel corporation (20250112120). INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Intel corporation (20250113559). TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER
- Intel corporation (20250113595). MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL LAYOUT EFFECT TUNING
- Intel corporation (20250142870). FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Intel corporation (20250142948). INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS
