18471402. STACKED MEMORY LAYERS WITH UNIFORM ACCESS (Intel Corporation)
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
Organization Name
Inventor(s)
Abhishek A. Sharma of Portland OR US
Sagar Suthram of Portland OR US
Wilfred Gomes of Portland OR US
Pushkar Sharad Ranade of San Jose CA US
Anand S. Murthy of Portland OR US
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
This abstract first appeared for US patent application 18471402 titled 'STACKED MEMORY LAYERS WITH UNIFORM ACCESS
Original Abstract Submitted
An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.
