SK hynix Inc. patent applications published on December 14th, 2023

Patent applications for SK hynix Inc. on December 14th, 2023

PIM COMPUTING SYSTEM AND PIM COMPUTATION OFFLOADING METHOD THEREOF (18069026)

Main Inventor

Seon Wook KIM

Brief explanation

The abstract describes a Processing-In-Memory (PIM) computing system and a method for offloading PIM computations using a DMA engine. The system includes a CPU, a memory with a PIM unit and a memory array (such as DRAM), and a DMA engine. The DMA engine processes transactions by handling descriptor requests and PIM requests for descriptors stored in memory, in response to memory requests from the CPU. The PIM unit performs PIM operations using data provided to the DMA engine in response to the descriptor requests.

• The patent application describes a PIM computing system and method for offloading PIM computations using a DMA engine.
• The system includes a CPU, a memory with a PIM unit and a memory array (e.g., DRAM), and a DMA engine.
• The DMA engine processes transactions by handling descriptor requests and PIM requests for descriptors stored in memory.
• The PIM unit performs PIM operations using data provided to the DMA engine in response to the descriptor requests.

Potential Applications

• High-performance computing: The PIM computing system can be used in applications that require high computational power, such as scientific simulations, data analytics, and machine learning.
• Edge computing: The system can be deployed in edge devices to offload PIM computations, enabling faster and more efficient processing of data at the edge.
• Internet of Things (IoT): The PIM computing system can be utilized in IoT devices to perform complex computations locally, reducing the need for data transmission and improving response time.

Problems Solved

• Offloading PIM computations: The system provides a method for offloading PIM computations from the CPU to the PIM unit, reducing the burden on the CPU and improving overall system performance.
• Efficient memory access: The DMA engine efficiently handles memory requests, allowing for faster data transfer between the CPU, PIM unit, and memory array.
• Enhanced processing capabilities: The PIM unit performs PIM operations using data provided by the DMA engine, enabling efficient and parallel processing within the memory itself.

Benefits

• Improved performance: Offloading PIM computations and utilizing the PIM unit within the memory array can significantly enhance overall system performance and reduce processing time.
• Reduced CPU load: By offloading computations to the PIM unit, the CPU can focus on other tasks, improving system multitasking capabilities.
• Energy efficiency: The PIM computing system reduces data movement between the CPU and memory, resulting in lower energy consumption and improved energy efficiency.

Abstract

A Processing-In-Memory (PIM) computing system and a PIM computation offloading method thereof perform PIM computation offloading using a DMA engine. The DMA engine is configured to process a transaction by respectively performing descriptor requests and PIM requests for one or more descriptors stored in a memory, in response to a memory request of a CPU. The memory includes a PIM unit and a memory array, which memory array may be a DRAM. In response to the PIM requests, the PIM unit performs PIM operations using information included in data provided to the DMA engine in response to the descriptor requests.

SEMICONDUCTOR APPARATUS WITH PROGRAM OPERATION CONTROL (17983115)

Main Inventor

Hyung Jin CHOI

Brief explanation

The patent application describes a semiconductor apparatus that includes a memory cell array and a control circuit. The control circuit is designed to perform a program operation on specific cells within the memory cell array, using a series of loops. 

• The control circuit applies a bit line voltage to the bit lines during the program operation.
• The bit line voltage has a predetermined level in loops where a pass voltage with a lower level is applied.
• In loops where a pass voltage with a higher level is applied, the control circuit applies a bit line voltage that is higher than the predetermined level.

Potential applications of this technology:

• Memory devices: This semiconductor apparatus can be used in various memory devices, such as flash memory or non-volatile memory, to improve the efficiency and accuracy of program operations.

Problems solved by this technology:

• Efficient programming: By applying different bit line voltages based on the pass voltage level, the control circuit ensures efficient programming of the target cells in the memory cell array.

Benefits of this technology:

• Improved performance: The use of different bit line voltages based on the pass voltage level allows for more precise and efficient program operations, leading to improved overall performance of the semiconductor apparatus.
• Enhanced reliability: By applying the appropriate bit line voltage, the control circuit ensures that the target cells are programmed accurately, reducing the risk of errors or data corruption.

Abstract

A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

COMPUTING SYSTEM AND METHOD OF OPERATING THE SAME (18081519)

Main Inventor

Jeong Ho JEON

Brief explanation

The present technology is related to an electronic device that includes a garbage collection controller and an idle time processor. The garbage collection controller sends commands to a storage device to request health information, garbage collection cost information, and to instruct the storage device to perform garbage collection. The idle time processor processes information on the idle time of the storage device.

• The electronic device includes a garbage collection controller and an idle time processor.
• The garbage collection controller sends commands to the storage device to request health information.
• The health information includes the host write amount and the storage device write amount.
• The garbage collection controller also requests garbage collection cost information based on the health information.
• The garbage collection controller instructs the storage device to perform garbage collection based on the garbage collection cost information and the idle time of the storage device.
• The idle time processor processes information on the idle time of the storage device.

Potential Applications

• This technology can be applied in electronic devices that use storage devices, such as computers, smartphones, and tablets.
• It can be used to optimize the garbage collection process in storage devices, improving their performance and efficiency.

Problems Solved

• The technology solves the problem of inefficient garbage collection in storage devices.
• It addresses the issue of storage devices becoming slow or unresponsive due to excessive garbage collection operations.

Benefits

• The technology improves the performance and efficiency of storage devices.
• It helps to prolong the lifespan of storage devices by optimizing garbage collection operations.
• It enhances the overall user experience by preventing slowdowns and unresponsiveness in electronic devices.

Abstract

The present technology relates to an electronic device. According to the present technology, a host device may include a garbage collection controller and an idle time processor. The garbage collection controller may provide, to a storage device, a health information request command for requesting health information including a host write amount and a storage device write amount, provide, to the storage device, a first garbage collection control command for requesting garbage collection cost information based on the health information, provide, to the storage device, a second garbage collection control command for instructing to perform garbage collection based on the garbage collection cost information and an idle time of the storage device. The idle time processor may process information on the idle time.

SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS (18053003)

Main Inventor

Dong Hyuk KIM

Brief explanation

The patent application describes a unit page buffer block that consists of multiple page buffer pairs, each including a common column decoder block, an upper page buffer stage, and a lower page buffer stage.

• Each page buffer pair has a common column decoder block and upper and lower page buffer stages.
• The upper page buffer stage includes an upper selection block, an upper latch block, and an upper cache block.
• The lower page buffer stage includes a lower selection block, a lower latch block, and a lower cache block.
• The upper selection block consists of four sub-selection blocks.
• The upper and lower latch blocks consist of twelve upper sub-latch blocks.
• The upper and lower cache blocks consist of twelve upper sub-cache blocks.
• The common column decoder block includes three sub-common column decoder blocks arranged in a row direction.

Potential applications of this technology:

• Memory systems in computers, smartphones, and other electronic devices.
• Data storage and retrieval in databases and cloud computing.

Problems solved by this technology:

• Efficient and reliable data storage and retrieval in memory systems.
• Improved performance and speed of memory operations.

Benefits of this technology:

• Enhanced memory capacity and efficiency.
• Faster data access and retrieval.
• Improved overall system performance.

Abstract

A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

APPARATUS AND METHOD FOR READING DATA BASED ON A PROGRAM STATUS OF A NON-VOLATILE MEMORY DEVICE (17965369)

Main Inventor

Kang Woo PARK

Brief explanation

The abstract describes a memory device that includes a memory group with multiple memory cells, a control circuitry, and a page buffer circuit. The control circuitry reads both a first hard decision data entry and a first soft decision data entry from a specific memory cell. The page buffer circuit consists of multiple data latches to store the hard and soft decision data entries, as well as at least one cache latch to store one of these data entries transferred from the data latches.

• The memory device has a memory group with multiple memory cells.
• The control circuitry reads both hard and soft decision data entries from a specific memory cell.
• The page buffer circuit includes data latches to store the hard and soft decision data entries.
• The page buffer circuit also includes a cache latch to store one of the data entries transferred from the data latches.

Potential Applications

• This memory device can be used in various electronic devices such as computers, smartphones, and tablets.
• It can be utilized in data storage systems, improving the efficiency and reliability of memory operations.

Problems Solved

• The memory device solves the problem of efficiently reading both hard and soft decision data entries from a memory cell.
• It addresses the challenge of storing and transferring the data entries within the page buffer circuit.

Benefits

• The memory device allows for simultaneous reading of hard and soft decision data entries, enhancing data retrieval speed.
• It provides efficient storage and transfer of data entries within the page buffer circuit, optimizing memory operations.
• The device improves the overall performance and reliability of memory systems.

Abstract

A memory device includes a memory group comprising plural memory cells, a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plural memory cells, and a page buffer circuit, coupled to the first memory cell via a bit line. The page buffer circuit includes plural data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plural data latches.

SEMICONDUCTOR SYSTEM FOR PERFORMING A DUTY RATIO ADJUSTMENT OPERATION (17968374)

Main Inventor

Sang Geun BAE

Brief explanation

The patent application describes a semiconductor system consisting of two semiconductor devices. The first device generates a clock and pattern data, receives a strobe signal, and outputs data. It also adjusts the duty ratio of the strobe signal by comparing odd and even data generated from the output data and pattern data. The second device stores the pattern data, outputs the clock as the strobe signal by adjusting its duty ratio, and outputs the stored pattern data as the output data.

• The first semiconductor device generates a clock and pattern data.
• It receives a strobe signal and outputs data.
• It adjusts the duty ratio of the strobe signal by comparing odd and even data.
• The second semiconductor device stores the pattern data.
• It outputs the clock as the strobe signal by adjusting its duty ratio.
• It outputs the stored pattern data as the output data.

Potential Applications

• This semiconductor system can be used in various electronic devices that require precise timing and data synchronization.
• It can be applied in communication systems, data storage devices, and high-speed data processing systems.

Problems Solved

• The system solves the problem of maintaining accurate timing and synchronization between different semiconductor devices.
• It addresses the issue of adjusting the duty ratio of the strobe signal to ensure reliable data transmission.

Benefits

• The system provides precise timing and synchronization between semiconductor devices, improving overall system performance.
• It allows for the adjustment of the duty ratio of the strobe signal, ensuring reliable and efficient data transmission.
• The system simplifies the design and implementation of semiconductor systems by integrating clock generation, data storage, and data output functions.

Abstract

A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

MEMORY SYSTEM (18358587)

Main Inventor

Woongrae KIM

Brief explanation

The patent application describes a memory system that includes two memory areas: a normal memory area for storing regular data and a security memory area for storing sensitive data. 

• The system includes a first row hammer detection circuit that samples and counts the number of rows activated in the normal memory area. This circuit identifies the first rows that need to be refreshed to prevent data corruption caused by row hammer attacks.
• Additionally, the system includes a second row hammer detection circuit that counts all the rows activated in the security memory area. This circuit identifies the second rows that need to be refreshed to ensure the security of the sensitive data.
• The purpose of these row hammer detection circuits is to prevent row hammer attacks, which exploit the vulnerability of DRAM cells to repeated access, causing bit flips and potentially compromising data integrity and security.

Potential applications of this technology:

• This memory system can be used in various computing devices, such as computers, servers, and mobile devices, to protect both regular and sensitive data from row hammer attacks.
• It can be particularly useful in systems that handle sensitive information, such as financial institutions, government agencies, and data centers.

Problems solved by this technology:

• Row hammer attacks can lead to data corruption and security breaches, compromising the integrity and confidentiality of stored information.
• This memory system addresses the vulnerability of DRAM cells to row hammer attacks by detecting and refreshing the rows that are susceptible to such attacks.

Benefits of this technology:

• By incorporating row hammer detection circuits, the memory system provides an additional layer of protection against row hammer attacks, enhancing data integrity and security.
• The system ensures that both regular and sensitive data are safeguarded from the potential consequences of row hammer attacks.
• It offers a more efficient and targeted approach to refreshing memory rows, reducing the overall system overhead and improving performance.

Abstract

A memory system includes: a normal memory area suitable for storing normal data; a security memory area suitable for storing security data; a first row hammer detection circuit suitable for sampling and counting a portion of rows that are activated in the normal memory area to select first rows that need to be refreshed; and a second row hammer detection circuit suitable for counting all rows that are activated in the security memory area to select second rows that need to be refreshed.

SEMICONDUCTOR MEMORY DEVICE INCLUDING CHALCOGENIDE (18060884)

Main Inventor

Jong Ho LEE

Brief explanation

Abstract:

A semiconductor memory device is described that includes a memory cell with a chalcogenide layer composed of three or more components. The memory cell is positioned between a first electrode and a second electrode. The device also includes a peripheral circuit that provides the memory cell with a program pulse, which induces a compositional gradient in the chalcogenide layer.

Patent/Innovation Explanation:

• The semiconductor memory device includes a memory cell with a chalcogenide layer composed of three or more components.
• The memory cell is positioned between a first electrode and a second electrode.
• A peripheral circuit is included in the device to provide the memory cell with a program pulse.
• The program pulse induces a compositional gradient in the chalcogenide layer.

Potential Applications:

• This technology can be used in various memory devices, such as non-volatile memory (NVM) devices.
• It can be applied in computer systems, smartphones, tablets, and other electronic devices that require memory storage.

Problems Solved:

• The technology addresses the need for improved memory devices with enhanced performance and reliability.
• It solves the problem of achieving a compositional gradient in the chalcogenide layer of a memory cell.

Benefits of this Technology:

• The use of a chalcogenide layer with three or more components improves the performance and reliability of the memory device.
• The induced compositional gradient in the chalcogenide layer enhances the functionality and efficiency of the memory cell.
• The technology enables faster and more efficient data storage and retrieval in electronic devices.

Abstract

A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME (17972224)

Main Inventor

Jong Kyung PARK

Brief explanation

The abstract describes a memory device and a method of operating it. Here is a simplified explanation of the abstract:

• The memory device consists of multiple memory cell strings, a peripheral circuit, and an operation controller.
• The peripheral circuit is responsible for performing read operations on selected memory cells using different read voltages.
• The operation controller controls the peripheral circuit to perform the read operation using a first read voltage, a first potential adjustment operation, and then a second read voltage that is lower than the first read voltage.
• The first potential adjustment operation involves applying a first turn-on voltage to unselected source select lines connected to unselected memory cell strings for a specific period and then applying a ground voltage to those unselected source select lines.

Potential applications of this technology:

• Memory devices using this method can be used in various electronic devices such as smartphones, tablets, and computers.
• It can be applied in data storage systems, improving the performance and efficiency of memory operations.

Problems solved by this technology:

• The method allows for more efficient read operations by using different read voltages and a potential adjustment operation.
• It helps to reduce power consumption and improve the overall performance of the memory device.

Benefits of this technology:

• Improved read operation efficiency and accuracy.
• Reduced power consumption.
• Enhanced performance and reliability of memory devices.

Abstract

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cell strings, a peripheral circuit configured to, using a plurality of read voltages, perform a read operation that reads data that is stored in a selected memory cell that is included in a selected memory cell string, and an operation controller configured to control the peripheral circuit to perform the read operation by using a first read voltage, a first potential adjustment operation, and the read operation by using a second read voltage that is lower than the first read voltage, wherein the first potential adjustment operation is an operation that applies a first turn-on voltage to unselected source select lines that are coupled to unselected memory cell strings for a first period and thereafter applies a ground voltage to the unselected source select lines.

PAGE BUFFER CIRCUIT, METHOD OF OPERATING A SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM (18073340)

Main Inventor

Hyung Jin CHOI

Brief explanation

The abstract describes a page buffer circuit that includes a data latch circuit and a sensing latch circuit. The data latch circuit is responsible for storing data during normal operation, while the sensing latch circuit receives and stores the data from the data latch circuit during a suspend operation. The sensing latch circuit then transmits the stored data back to the data latch circuit during a sensing operation. Additionally, the sensing latch circuit can suspend data in a memory cell and output the suspended data.

• The page buffer circuit includes a data latch circuit and a sensing latch circuit.
• The data latch circuit stores data during normal operation.
• The sensing latch circuit receives and stores data from the data latch circuit during a suspend operation.
• The sensing latch circuit transmits the stored data back to the data latch circuit during a sensing operation.
• The sensing latch circuit can also suspend data in a memory cell and output the suspended data.

Potential Applications

• This technology can be applied in various memory systems, such as computer memory or storage devices.
• It can be used in systems that require efficient data storage and retrieval during suspend operations.

Problems Solved

• The page buffer circuit solves the problem of efficiently storing and retrieving data during suspend operations.
• It addresses the need for a circuit that can suspend data in a memory cell and output the suspended data.

Benefits

• The page buffer circuit provides a reliable and efficient solution for storing and retrieving data during suspend operations.
• It allows for seamless transition between normal operation and suspend operation.
• The circuit enables efficient memory management and data transfer in memory systems.

Abstract

A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.

SEMICONDUCTOR PACKAGES INCLUDING AT LEAST ONE DIE POSITION CHECKER (18450143)

Main Inventor

Bok Gyu MIN

Brief explanation

The abstract describes a semiconductor package that includes multiple dies stacked on top of each other. The package also includes a position checker that indicates the allowable range for the position of one of the dies.

• The semiconductor package includes multiple dies stacked on top of each other.
• The package substrate holds the dies in place.
• A position checker is included on the package substrate.
• The position checker indicates the allowable range for the position of one of the dies.
• The position checker helps ensure that the first die is located within the specified range.

Potential Applications

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit packaging

Problems Solved

• Ensures proper positioning of dies in a semiconductor package
• Helps prevent misalignment or damage during assembly

Benefits

• Improved manufacturing efficiency
• Enhanced product reliability
• Reduced risk of assembly errors

Abstract

A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

CHARGE PUMP CIRCUIT RELATED TO OVERVOLTAGE (18097862)

Main Inventor

Giovanni BELLOTTI

Brief explanation

The abstract describes a charge pump circuit that boosts a supply voltage to provide higher voltages at its output terminals. It includes a first charge pump that boosts the supply voltage to provide a first charge pump voltage, and a second charge pump that further boosts the first charge pump voltage to provide a second charge pump voltage. The circuit also includes a voltage drop sensing device that detects drops in the first charge pump voltage and deactivates certain transistors when a drop is detected.

• The circuit includes a first charge pump that boosts the supply voltage.
• The first charge pump provides a first charge pump voltage at its output terminal.
• A second charge pump is connected to the output terminal of the first charge pump.
• The second charge pump further boosts the first charge pump voltage.
• The second charge pump provides a second charge pump voltage at its output terminal.
• A voltage drop sensing device is included in the circuit.
• The voltage drop sensing device detects drops in the first charge pump voltage.
• When a drop in the first charge pump voltage is detected, the voltage drop sensing device deactivates certain transistors of bypass units associated with the disabled charge pump stages.

Potential applications of this technology:

• Power management systems in electronic devices.
• Voltage boosting in battery-powered devices.
• Voltage regulation in integrated circuits.

Problems solved by this technology:

• Efficiently boosting supply voltage to higher levels.
• Detecting and compensating for drops in the charge pump voltage.
• Preventing damage to the circuit due to voltage drops.

Benefits of this technology:

• Improved power management efficiency.
• Enhanced voltage regulation.
• Protection against voltage drops and potential circuit damage.

Abstract

A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.

RANDOM PULSE GENERATOR AND MEMORY (17976096)

Main Inventor

Hong Ki Moon

Brief explanation

The abstract describes a random pulse generator that includes several components to generate random pulses. 

• Randomness test circuit: This circuit is used to test the randomness of a random pulse.
• Control circuit: This circuit generates frequency control information and pulse control information based on the test result from the randomness test circuit.
• Periodic wave generating circuit: This circuit generates a periodic wave with a frequency that can be adjusted using the frequency control information.
• Pulse generating circuit: This circuit generates the random pulse using the periodic wave and the pulse control information.

Potential applications of this technology:

• Random number generation: The random pulse generator can be used in applications that require random number generation, such as cryptography, simulations, and gaming.
• Testing and analysis: The randomness test circuit can be used to test and analyze the randomness of various systems and processes.

Problems solved by this technology:

• Lack of randomness: The random pulse generator provides a solution for generating random pulses, which can be used to address the problem of lack of randomness in certain applications.
• Inadequate testing methods: The randomness test circuit allows for testing the randomness of random pulses, providing a more accurate and reliable method compared to traditional testing approaches.

Benefits of this technology:

• Improved security: The random pulse generator can enhance the security of systems that rely on random number generation, such as encryption algorithms.
• Enhanced accuracy: The randomness test circuit ensures that the generated random pulses are truly random, improving the accuracy and reliability of applications that depend on random data.
• Versatile applications: The random pulse generator can be used in a wide range of applications that require random number generation or testing of randomness.

Abstract

A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME (18056676)

Main Inventor

Shin-Hyun JEONG

Brief explanation

The abstract describes a phase mixing circuit for a multi-phase signal. The circuit includes a jitter cancellation circuit and a delay adjustment circuit.

• The jitter cancellation circuit mixes phases of two input signals to produce two output signals.
• The delay adjustment circuit adjusts the delays of the output signals to produce two additional output signals.
• The circuit can be used to mix and adjust the phases of multi-phase signals.
• The circuit helps cancel out jitter in the input signals.
• The circuit allows for precise control and adjustment of signal delays.
• The circuit can be used in various applications that require phase mixing and delay adjustment, such as communication systems, signal processing, and data transmission.
• The circuit solves the problem of phase mismatch and jitter in multi-phase signals.
• The circuit provides the benefit of improved signal quality and accuracy.
• The circuit allows for more precise control and manipulation of multi-phase signals.
• The circuit can enhance the performance of communication systems and signal processing applications.

Abstract

A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

APPARATUS FOR CONTROLLING IN-RUSH CURRENT AND AN OPERATION METHOD THEREOF (17966075)

Main Inventor

Suk Hwan CHOI

Brief explanation

The patent application describes a power circuit that includes regulators and in-rush current controllers. The regulators adjust the input voltage to generate internal power voltages, while the in-rush current controllers provide the input voltage to the regulators.

• The regulators in the power circuit adjust the input voltage to generate multiple internal power voltages.
• The in-rush current controllers provide the input voltage to the regulators, which corresponds to an increasement voltage.
• The increasement voltage rises at a preset rate until all the internal power voltages reach a target level.

Potential Applications

• Power circuits in electronic devices and appliances.
• Power management systems in industrial equipment.
• Power supply units in telecommunications infrastructure.

Problems Solved

• In-rush current controllers help prevent excessive current flow during power-up, protecting the circuit and components.
• Regulators ensure stable and adjustable internal power voltages for various applications.
• The preset rate of increasement voltage helps control the power-up process and avoid voltage spikes.

Benefits

• Improved circuit protection and reliability.
• Efficient power management and voltage regulation.
• Enhanced control over the power-up process.
• Suitable for a wide range of electronic devices and industrial equipment.

Abstract

A power circuit includes a plurality of regulators and a plurality of in-rush current controllers. The plurality of regulators is coupled to an external power voltage and configured to adjust a level of an input voltage to generate a plurality of internal power voltages. The plurality of in-rush current controllers is configured to provide the input voltage to the plurality of regulators, the input voltage corresponding to an increasement voltage. The increasement voltage has a level rising at a preset rate until the plurality of internal power voltages all reach a target level.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME (17993473)

Main Inventor

Dong Soo KIM

Brief explanation

The present invention relates to a semiconductor device and a method of fabricating the same. The device includes a substrate with a trench, a gate dielectric layer formed along the sidewall and bottom surface of the trench, a lower gate electrode made of a first metal nitride with a first grain size, an upper gate electrode partially filling the trench and made of a second metal nitride with a second grain size larger than the first grain size, and a capping layer filling the remaining portion of the trench.

• The semiconductor device includes a trench structure with improved electrical characteristics.
• The gate dielectric layer enhances the performance of the device.
• The lower gate electrode made of a first metal nitride provides stability and conductivity.
• The upper gate electrode made of a second metal nitride with a larger grain size improves the device's performance.
• The capping layer fills the remaining trench space, providing protection and stability to the device.

Potential Applications

This technology can be applied in various semiconductor devices, including but not limited to:

• Integrated circuits (ICs)
• Transistors
• Memory devices
• Microprocessors

Problems Solved

The semiconductor device and fabrication method address the following issues:

• Improving electrical characteristics of the device
• Enhancing stability and conductivity of the gate electrodes
• Optimizing performance by utilizing different metal nitrides with varying grain sizes
• Providing protection and stability to the device through the capping layer

Benefits

The use of this technology offers several advantages:

• Improved electrical characteristics of the semiconductor device
• Enhanced stability and conductivity of the gate electrodes
• Better performance due to the utilization of different metal nitrides with varying grain sizes
• Increased protection and stability provided by the capping layer

Abstract

Embodiments of the present invention provides a semiconductor device with improved electrical characteristics and a method of fabricating the same. A semiconductor device according to an embodiment of the present invention comprises: a substrate including a trench; a gate dielectric layer formed along a sidewall surface and a bottom surface of the trench; a lower gate electrode filling a lower portion of the trench over the gate dielectric layer and formed of a first metal nitride, the first metal nitride having a first grain size; an upper gate electrode partially filling the trench over the lower gate electrode, including a low work function control element, and formed of a second metal nitride, the second metal nitride having a second grain size bigger than the first grain size; and a capping layer gap-filling the remainder of the trench over the upper gate electrode.

VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE VERTICAL SEMICONDUCTOR DEVICE (18446827)

Main Inventor

In-Su PARK

Brief explanation

The abstract describes a vertical semiconductor device that includes a lower structure, a multi-layer stack structure, a vertical structure, a vertical source line, and a horizontal source channel contact.

• The lower structure serves as a foundation for the device.
• The multi-layer stack structure consists of a source layer and gate electrodes.
• The vertical structure penetrates the multi-layer stack structure and includes a channel layer that is insulated from the source layer.
• The vertical source line is spaced apart from the vertical structure and contacts the source layer.
• The horizontal source channel contact connects the source layer and the channel layer and includes two conductive layers with different dopants.

Potential Applications

• This technology can be used in various electronic devices such as transistors, integrated circuits, and memory devices.
• It can be applied in the field of telecommunications, computing, and consumer electronics.

Problems Solved

• The vertical semiconductor device solves the problem of efficient vertical integration of different layers in a semiconductor structure.
• It addresses the challenge of achieving proper electrical connections between the source layer and the channel layer.

Benefits

• The vertical semiconductor device allows for compact and efficient integration of multiple layers, leading to improved performance and functionality.
• The use of different dopants in the horizontal source channel contact enhances the device's electrical properties and enables precise control over its operation.
• The technology offers potential cost savings in manufacturing processes due to its simplified structure and improved efficiency.

Abstract

A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE (18450865)

Main Inventor

Nam Jae LEE

Brief explanation

The patent application describes a semiconductor device and its manufacturing method. The device includes a stack structure, a source structure, a channel structure, and a first memory layer.

• The semiconductor device has a stack structure, source structure, channel structure, and a first memory layer.
• The source structure includes a protrusion part between the first memory layer and the channel structure.
• The channel structure penetrates the stack structure and is connected to the source structure.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
• It can be utilized in memory storage devices, processors, and other integrated circuits.

Problems solved by this technology:

• The inclusion of the first memory layer improves the performance and functionality of the semiconductor device.
• The protrusion part in the source structure enhances the connection between the first memory layer and the channel structure.

Benefits of this technology:

• The stack structure and source structure provide a compact and efficient design for the semiconductor device.
• The improved connection between the first memory layer and the channel structure enhances the overall performance and reliability of the device.

Abstract

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure; a source structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure. The source structure includes a first protrusion part protruding between the first memory layer and the channel structure.