18056676. PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME simplified abstract (SK hynix Inc.)

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PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME

Organization Name

SK hynix Inc.

Inventor(s)

Shin-Hyun Jeong of Seoul (KR)

Yongun Jeong of Seoul (KR)

Suhwan Kim of Seoul (KR)

PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18056676 titled 'PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME

Simplified Explanation

The abstract describes a phase mixing circuit for a multi-phase signal. The circuit includes a jitter cancellation circuit and a delay adjustment circuit.

  • The jitter cancellation circuit mixes phases of two input signals to produce two output signals.
  • The delay adjustment circuit adjusts the delays of the output signals to produce two additional output signals.
  • The circuit can be used to mix and adjust the phases of multi-phase signals.
  • The circuit helps cancel out jitter in the input signals.
  • The circuit allows for precise control and adjustment of signal delays.
  • The circuit can be used in various applications that require phase mixing and delay adjustment, such as communication systems, signal processing, and data transmission.
  • The circuit solves the problem of phase mismatch and jitter in multi-phase signals.
  • The circuit provides the benefit of improved signal quality and accuracy.
  • The circuit allows for more precise control and manipulation of multi-phase signals.
  • The circuit can enhance the performance of communication systems and signal processing applications.


Original Abstract Submitted

A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

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