18053003. SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS simplified abstract (SK hynix Inc.)

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SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS

Organization Name

SK hynix Inc.

Inventor(s)

Dong Hyuk Kim of Icheon-si (KR)

Tae Sung Park of Icheon-si (KR)

Sang Hyun Sung of Icheon-si (KR)

Sung Lae Oh of Icheon-si (KR)

Soo Nam Jung of Icheon-si (KR)

SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18053003 titled 'SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS

Simplified Explanation

The patent application describes a unit page buffer block that consists of multiple page buffer pairs, each including a common column decoder block, an upper page buffer stage, and a lower page buffer stage.

  • Each page buffer pair has a common column decoder block and upper and lower page buffer stages.
  • The upper page buffer stage includes an upper selection block, an upper latch block, and an upper cache block.
  • The lower page buffer stage includes a lower selection block, a lower latch block, and a lower cache block.
  • The upper selection block consists of four sub-selection blocks.
  • The upper and lower latch blocks consist of twelve upper sub-latch blocks.
  • The upper and lower cache blocks consist of twelve upper sub-cache blocks.
  • The common column decoder block includes three sub-common column decoder blocks arranged in a row direction.

Potential applications of this technology:

  • Memory systems in computers, smartphones, and other electronic devices.
  • Data storage and retrieval in databases and cloud computing.

Problems solved by this technology:

  • Efficient and reliable data storage and retrieval in memory systems.
  • Improved performance and speed of memory operations.

Benefits of this technology:

  • Enhanced memory capacity and efficiency.
  • Faster data access and retrieval.
  • Improved overall system performance.


Original Abstract Submitted

A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

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