|
|
| Line 1: |
Line 1: |
| − | '''Summary of the patent applications from NANYA TECHNOLOGY CORPORATION on November 30th, 2023'''
| |
| − |
| |
| − | NANYA TECHNOLOGY CORPORATION has recently filed patents related to semiconductor devices and manufacturing methods. These patents describe various features and structures of semiconductor devices, as well as methods for their fabrication. Notable applications include a semiconductor device with a programmable feature, a memory structure with a unique contact design, a semiconductor device with multiple layers and components, and a method for preparing a memory device with improved performance and efficiency.
| |
| − |
| |
| − | In the semiconductor device with a programmable feature, the device includes a substrate, conductive lines, conductive features, and memory cells. The substrate has two islands separated by an isolation structure, with the first island being smaller in size than the second island. The conductive lines and features connect the islands and provide electrical connectivity for the memory cells.
| |
| − |
| |
| − | The memory structure patent describes a contact design with three portions extending into different layers. The first contact portion is lower than the source/drain region, and the second contact portion is located between the first and third contact portions. The specific distance between the sidewalls of the first contact portion and the source/drain region is also mentioned.
| |
| − |
| |
| − | The semiconductor device patent discusses a device with various layers and components, including a substrate, dielectric layers, and metallization layers. The metallization layers surround channel layers, and the first metallization layer has a protruding portion that extends towards the second metallization layer.
| |
| − |
| |
| − | The method for preparing a memory device involves forming bottom and top cells within substrates, with common bit lines connecting them. The aim is to improve the performance and efficiency of the memory device.
| |
| − |
| |
| − | In terms of notable applications, the patents describe methods for manufacturing semiconductor devices using substrates with different islands, insulative layers for protection, conductive features for connectivity, and specific patterning and layering techniques. The patents also highlight the use of multiple dielectric layers in storage capacitors to enhance their performance.
| |
| − |
| |
| − | - Semiconductor device with a programmable feature
| |
| − | - Memory structure with a unique contact design
| |
| − | - Semiconductor device with multiple layers and components
| |
| − | - Method for preparing a memory device with improved performance and efficiency
| |
| − | - Methods for manufacturing semiconductor devices using substrates with different islands, insulative layers, and conductive features
| |
| − | - Use of multiple dielectric layers in storage capacitors for enhanced performance.
| |
| − |
| |
| − |
| |
| − |
| |
| − |
| |
| | ==Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023== | | ==Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023== |
| | | | |
| Line 32: |
Line 8: |
| | Chih-Jen Chen | | Chih-Jen Chen |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a voltage regulator for providing a word line voltage.
| |
| − | * The voltage regulator includes a voltage divider, a comparator, a boost circuit, and a bypass transistor.
| |
| − | * The voltage divider is connected between the word line voltage and a low reference voltage.
| |
| − | * The voltage divider consists of resistive elements connected in series at intermediate nodes.
| |
| − | * The comparator generates an enable signal based on the voltage value on a divided intermediate node.
| |
| − | * The boost circuit increases the word line voltage when the enable signal is received.
| |
| − | * The bypass transistor is connected between two intermediate nodes and is turned off when a control signal reaches a specific voltage value on the first intermediate node.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A voltage regulator for providing a word line voltage is provided. The voltage regulator includes a voltage divider, a comparator, a boost circuit and a bypass transistor. The voltage divider is coupled between the word line voltage and a low reference voltage. The voltage divider includes resistive elements connected in series at intermediate nodes. The comparator provides an enable signal according to a divided voltage value on a divided intermediate node among the intermediate nodes. The boost circuit boosts the word line voltage in response to the enable signal. A source terminal of the bypass transistor is connected to a first intermediate node among the intermediate nodes. A drain terminal of the bypass transistor is connected to a second intermediate node among the intermediate nodes. The bypass transistor is turned-off in response to the control signal having an intermediate voltage value on the first intermediate node.
| |
| | | | |
| | ===MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824011. MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824011]])=== | | ===MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824011. MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824011]])=== |
| Line 52: |
Line 16: |
| | JAR-MING HO | | JAR-MING HO |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory device with multiple layers and channels.
| |
| − |
| |
| − | * The memory device includes a substrate, a dielectric layer, and multiple metallization layers and channel layers.
| |
| − | * The dielectric layer is placed on the substrate.
| |
| − | * The first metallization layer is located within the dielectric layer and extends in a specific direction.
| |
| − | * The first channel layer is surrounded by the first metallization layer.
| |
| − | * Similarly, the second metallization layer is also within the dielectric layer and extends in the same direction.
| |
| − | * The second channel layer is surrounded by the second metallization layer.
| |
| − | * The first metallization layer has a protruding portion that extends towards the second metallization layer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME ([[US Patent Application 18231912. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME simplified abstract|18231912]])=== | | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME ([[US Patent Application 18231912. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME simplified abstract|18231912]])=== |
| Line 74: |
Line 24: |
| | CHENG-HSIANG FAN | | CHENG-HSIANG FAN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a semiconductor device structure and a method for forming it.
| |
| − | - The purpose of the invention is to prevent the collapse of fine patterns in the semiconductor device structure.
| |
| − | - The structure includes a first target structure and a second target structure on a semiconductor substrate.
| |
| − | - A first spacer element is placed over the first target structure.
| |
| − | - The topmost point of the first spacer element is positioned between the central lines of the first and second target structures in a cross-sectional view.
| |
| − | - The invention aims to provide a solution for maintaining the integrity of fine patterns in semiconductor devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which prevents the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.
| |
| | | | |
| | ===METHOD OF PREPARING ACTIVE AREAS ([[US Patent Application 17828802. METHOD OF PREPARING ACTIVE AREAS simplified abstract|17828802]])=== | | ===METHOD OF PREPARING ACTIVE AREAS ([[US Patent Application 17828802. METHOD OF PREPARING ACTIVE AREAS simplified abstract|17828802]])=== |
| Line 93: |
Line 32: |
| | YING-CHENG CHUANG | | YING-CHENG CHUANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present disclosure describes a method for preparing active areas on a substrate.
| |
| − | * The method involves receiving a substrate with an oxide layer, a nitride layer, and a silicon layer.
| |
| − | * A patterned photoresist layer is formed on the silicon layer.
| |
| − | * A mask layer is deposited to cover the contour of the patterned photoresist layer.
| |
| − | * A carbon layer is coated on the mask layer.
| |
| − | * The carbon layer, mask layer, and silicon layer are etched to expose the top surface of the nitride layer.
| |
| − | * Multiple opens are formed in the oxide layer to expose the top surface of the substrate.
| |
| − | * An epitaxial layer is grown from the top surface of the substrate in the multiple opens to form the active areas.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.
| |
| | | | |
| | ===METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824481. METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824481]])=== | | ===METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824481. METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824481]])=== |
| Line 114: |
Line 40: |
| | CHIH-HSUAN YEH | | CHIH-HSUAN YEH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present disclosure describes a method for fabricating a semiconductor device using a photomask and a stack structure.
| |
| − | * The method involves providing a photomask that has an opaque layer and a translucent layer on a mask substrate.
| |
| − | * The translucent layer has a mask opening that exposes a portion of the mask substrate.
| |
| − | * A stack structure is then provided, which includes an etch stop layer, a bottom conductive layer, and a first inter-dielectric layer.
| |
| − | * A pre-process mask layer is formed on the stack structure.
| |
| − | * The pre-process mask layer is patterned using the photomask to create a patterned mask layer.
| |
| − | * The patterned mask layer includes a mask region corresponding to the opaque layer, a region of body portion corresponding to the translucent layer, and a hole of contact portion corresponding to the mask opening of contact portion.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method for fabricating a semiconductor device including providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate, wherein the translucent layer includes a mask opening of contact portion which exposes a portion of the mask substrate; providing a stack structure including an etch stop layer on a bottom conductive layer and a first inter-dielectric layer on the etch stop layer, and forming a pre-process mask layer on the stack structure; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a region of body portion corresponding to the translucent layer, and a hole of contact portion corresponding to the mask opening of contact portion.
| |
| | | | |
| | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER ([[US Patent Application 18232833. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER simplified abstract|18232833]])=== | | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER ([[US Patent Application 18232833. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER simplified abstract|18232833]])=== |
| Line 134: |
Line 48: |
| | JUNG-HSING CHIEN | | JUNG-HSING CHIEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device with composite pillars, a dielectric isolation structure, a sealing layer, and air spaces.
| |
| − | * The composite pillars consist of a conductive pillar and a dielectric cap.
| |
| − | * The dielectric isolation structure is placed between adjacent composite pillars and includes an air gap enclosed by a liner layer.
| |
| − | * The sealing layer is in contact with the top portion of the dielectric isolation structure and the top of the dielectric cap.
| |
| − | * Air spacers are formed between the sealing layer, the dielectric isolation structure, and the conductive pillar.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a semiconductor device including composite pillars, a dielectric isolation structure, a sealing layer, and air spaces. The composite pillars are disposed over a substrate. Each of the composite pillars include a conductive pillar and a dielectric cap over the conductive pillar. The dielectric isolation structure is disposed between adjacent two of the composite pillars. The dielectric isolation structure includes an air gap and a liner layer enclosing the air gap. The sealing layer is at least in contact with a top portion of the dielectric isolation structure and a top of the dielectric cap. The air spacers are formed between the sealing layer, the dielectric isolation structure and the conductive pillar.
| |
| | | | |
| | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP ([[US Patent Application 18232937. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP simplified abstract|18232937]])=== | | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP ([[US Patent Application 18232937. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP simplified abstract|18232937]])=== |
| Line 152: |
Line 56: |
| | LIANG-PIN CHOU | | LIANG-PIN CHOU |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for preparing a semiconductor device.
| |
| − | * The method involves forming two dielectric structures over a semiconductor substrate.
| |
| − | * A conductive material is then formed over the dielectric structures, extending into an opening between them.
| |
| − | * The conductive material is partially removed to create two bit lines in the opening.
| |
| − | * Capacitor contacts are formed in the dielectric structures.
| |
| − | * A sealing dielectric layer is formed over the bit lines, creating an air gap between the layer and the substrate.
| |
| − | * Finally, capacitors are formed over the capacitor contacts.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.
| |
| | | | |
| | ===MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17752642. MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17752642]])=== | | ===MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17752642. MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17752642]])=== |
| Line 172: |
Line 64: |
| | SHING-YIH SHIH | | SHING-YIH SHIH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method of manufacturing a semiconductor structure.
| |
| − | * The method involves providing a wafer with a substrate, a dielectric layer, and a conductive pad.
| |
| − | * A passivation layer is then applied over the substrate.
| |
| − | * Portions of the dielectric layer, substrate, and passivation layer are removed to expose the conductive pad.
| |
| − | * A conductive material and an elastic material are then placed within the exposed area.
| |
| − | * Portions of the conductive and elastic materials are removed to create an elastic member.
| |
| − | * Finally, a second conductive material is applied over the elastic member and the conductive material to create a conductive via surrounding the elastic member.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of manufacturing a semiconductor structure includes: providing a first wafer including a first substrate, a first dielectric layer under the first substrate, and a first conductive pad surrounded by the first dielectric layer; disposing a first passivation layer over the first substrate; removing portions of the first dielectric layer, the first substrate and the first passivation layer to form a first opening exposing a portion of the first conductive pad; disposing a first conductive material within the first opening; disposing a first elastic material within the first opening and surrounded by the first conductive material; removing portions of the first conductive material and the first elastic material adjacent to an end of the first opening to form a first elastic member; and disposing a second conductive material over the first elastic member and the first conductive material to form a first conductive via surrounding the first elastic member.
| |
| | | | |
| | ===SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17751941. SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17751941]])=== | | ===SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17751941. SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17751941]])=== |
| Line 192: |
Line 72: |
| | SHING-YIH SHIH | | SHING-YIH SHIH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor structure with an elastic member placed inside a via.
| |
| − | * The structure includes a wafer with a substrate, a dielectric layer beneath the substrate, and a conductive pad surrounded by the dielectric layer.
| |
| − | * A passivation layer is placed over the substrate.
| |
| − | * A conductive via extends from the conductive pad through the substrate, passivation layer, and partially through the dielectric layer.
| |
| − | * An elastic member is positioned within the conductive via.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a semiconductor structure having an elastic member within a via. The semiconductor structure includes a wafer including a substrate, a dielectric layer under the substrate, and a conductive pad surrounded by the dielectric layer; a passivation layer disposed over the substrate; a conductive via extending from the conductive pad through the substrate and the passivation layer and partially through the dielectric layer; and an elastic member disposed within the conductive via.
| |
| | | | |
| | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE ([[US Patent Application 18231254. METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE simplified abstract|18231254]])=== | | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE ([[US Patent Application 18231254. METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE simplified abstract|18231254]])=== |
| Line 210: |
Line 80: |
| | TZU-CHING TSAI | | TZU-CHING TSAI |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a circuit device with two substrates and barrier layers made of aluminum fluoride.
| |
| − | * The circuit device includes a first substrate with a first barrier layer and a second substrate with a second barrier layer.
| |
| − | * There are two conductive portions, one on each substrate, and they are covered by expanding pads.
| |
| − | * The first expanding pad is on the first conductive portion and has a larger contact area than the conductive portion.
| |
| − | * The second expanding pad is bonded to the first expanding pad and is on the second conductive portion, also with a larger contact area.
| |
| − | * The purpose of the expanding pads is to provide a larger contact area for improved connectivity.
| |
| − | * The use of aluminum fluoride in the barrier layers enhances the performance and durability of the circuit device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824012. SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824012]])=== | | ===SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824012. SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824012]])=== |
| Line 230: |
Line 88: |
| | CHIH-HSUAN YEH | | CHIH-HSUAN YEH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device with a contact structure.
| |
| − | * The device includes layers such as a bottom dielectric layer, a bottom conductive layer, an etch stop layer, and a first inter-dielectric layer.
| |
| − | * The contact structure consists of a body portion and a contact portion.
| |
| − | * The body portion is positioned along the first inter-dielectric layer and extends to the etch stop layer.
| |
| − | * The contact portion is located in the etch stop layer and makes contact with both the body portion and the bottom conductive layer.
| |
| − | * The body portion is wider than the contact portion.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application discloses a semiconductor device with a contact structure. The semiconductor device includes a bottom dielectric layer positioned on a substrate; a bottom conductive layer positioned in the bottom dielectric layer; an etch stop layer positioned on the bottom conductive layer; a first inter-dielectric layer positioned on the etch stop layer; and a contact structure including a body portion positioned along the first inter-dielectric layer and extending to the etch stop layer, and a contact portion positioned in the etch stop layer to and contacting the body portion and the bottom conductive layer. A width of the body portion is greater than a width of the contact portion.
| |
| | | | |
| | ===STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17751936. STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17751936]])=== | | ===STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17751936. STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17751936]])=== |
| Line 249: |
Line 96: |
| | KAI-HUNG LIN | | KAI-HUNG LIN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a storage capacitor with multiple dielectrics.
| |
| − | * The storage capacitor includes a lower electrode, an upper electrode, and three dielectric layers.
| |
| − | * The first dielectric layer covers the lower electrode.
| |
| − | * The second dielectric layer is placed on top of the first dielectric layer.
| |
| − | * The third dielectric layer is placed on top of the second dielectric layer.
| |
| − | * The upper electrode is placed on top of the third dielectric layer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a storage capacitor with multiple dielectrics. The storage capacitor includes a lower electrode, an upper electrode, a first dielectric layer, a second dielectric layer and a third dielectric layer. The first dielectric layer covers the lower electrode, the second dielectric layer is disposed on the first dielectric layer, and the third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.
| |
| | | | |
| | ===METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17752638. METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17752638]])=== | | ===METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17752638. METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17752638]])=== |
| Line 268: |
Line 104: |
| | KAI-HUNG LIN | | KAI-HUNG LIN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for creating a storage capacitor.
| |
| − | * Lower electrode is formed.
| |
| − | * A first dielectric layer is deposited to cover the lower electrode.
| |
| − | * A second dielectric layer is deposited on top of the first dielectric layer.
| |
| − | * A third dielectric layer is deposited on top of the second dielectric layer.
| |
| − | * An upper electrode is formed on top of the third dielectric layer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a method of fabricating a storage capacitor. The method includes steps of forming a lower electrode; depositing a first dielectric layer covering the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.
| |
| | | | |
| | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824487. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824487]])=== | | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824487. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824487]])=== |
| Line 287: |
Line 112: |
| | CHIN-TE KUO | | CHIN-TE KUO |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method of manufacturing a semiconductor device.
| |
| − | - The method involves providing a substrate and forming a conductive layer on it.
| |
| − | - The conductive layer is then patterned to create a first metallization layer and a second metallization layer that extend in a specific direction.
| |
| − | - The first metallization layer has a protruding portion that extends towards the second metallization layer.
| |
| − | - Within the first metallization layer, a first channel layer is formed, and within the second metallization layer, a second channel layer is formed.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.
| |
| | | | |
| | ===METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE ([[US Patent Application 17825480. METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE simplified abstract|17825480]])=== | | ===METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE ([[US Patent Application 17825480. METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE simplified abstract|17825480]])=== |
| Line 305: |
Line 120: |
| | YIN-FA CHEN | | YIN-FA CHEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method of manufacturing a semiconductor device.
| |
| − | - The method involves using a substrate with two islands, where the second island is larger than the first island.
| |
| − | - An insulative layer is deposited to cover the substrate.
| |
| − | - A conductive feature is formed that penetrates through the insulative layer and makes contact with the second island.
| |
| − | - A conductive line is then formed on top of the insulative layer and connected to the conductive feature.
| |
| − |
| |
| − | * The method aims to provide a manufacturing process for semiconductor devices.
| |
| − | * The use of two islands on the substrate allows for different areas and sizes.
| |
| − | * The insulative layer serves as a protective covering for the substrate.
| |
| − | * The conductive feature provides a connection to the larger second island.
| |
| − | * The conductive line allows for electrical connectivity in the semiconductor device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a method of manufacturing a semiconductor device. The method includes steps of providing a substrate comprising a first island and a second island, wherein the first island has a first area and the second island has a second area greater than the first area; depositing an insulative layer to cover the substrate; forming a conductive feature penetrating through the insulative layer and contacting the second island; and forming a conductive line on the insulative layer and connected to the conductive feature.
| |
| | | | |
| | ===METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824507. METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824507]])=== | | ===METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824507. METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824507]])=== |
| Line 329: |
Line 128: |
| | JAR-MING HO | | JAR-MING HO |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The present disclosure describes a method for preparing a memory device.
| |
| − | - The method involves forming a first bottom cell within a bottom substrate, which includes a bottom capacitor, a bottom word line, and a bottom channel layer.
| |
| − | - A first top cell is also formed within a top substrate, which includes a top capacitor, a top word line, and a top channel layer.
| |
| − | - A common bit line is formed between the first bottom cell and the first top cell, extending in a direction perpendicular to the bottom word line and top word line.
| |
| − | - The method aims to provide a memory device with improved performance and efficiency.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method for preparing a memory device. The method includes forming a first bottom cell within a bottom substrate, comprising: forming a first bottom capacitor within the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line. The method also includes forming a first top cell within a top substrate, comprising: forming a first top capacitor within the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first top channel layer surrounded by the first top word line. The method further includes forming a common bit line between the first bottom cell and the first top cell and extending along a second direction substantially perpendicular to the first direction.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825057. SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE simplified abstract|17825057]])=== | | ===SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825057. SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE simplified abstract|17825057]])=== |
| Line 347: |
Line 136: |
| | YIN-FA CHEN | | YIN-FA CHEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present application describes a semiconductor device and a semiconductor chip.
| |
| − | * The semiconductor device includes a substrate, a conductive line, a conductive feature, and a plurality of memory cells.
| |
| − | * The substrate consists of a first island, a second island, and an isolation structure between them.
| |
| − | * The first island has a smaller area compared to the second island.
| |
| − | * A conductive line is placed over the substrate.
| |
| − | * A conductive feature connects the conductive line to the second island.
| |
| − | * The plurality of memory cells are located in or on the first island.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a semiconductor device and a semiconductor chip. The semiconductor device includes a substrate, a conductive line, a conductive feature and a plurality of memory cells. The substrate includes a first island, a second island and an isolation structure, and the isolation structure is disposed between the first island and the second island. The first island has a first area, and the second island has a second area greater than the first area. The conductive line is disposed over the substrate. The conductive feature connects the conductive line to the second island. The plurality of memory cells are disposed in or on the first island.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824010. SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824010]])=== | | ===SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824010. SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824010]])=== |
| Line 367: |
Line 144: |
| | CHIN-TE KUO | | CHIN-TE KUO |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor device that includes various layers and components.
| |
| − | * The device includes a substrate, which serves as a base for the other layers.
| |
| − | * A dielectric layer is placed on top of the substrate.
| |
| − | * Within the dielectric layer, there is a first metallization layer that extends in a specific direction.
| |
| − | * The first metallization layer surrounds a first channel layer.
| |
| − | * Similarly, there is a second metallization layer within the dielectric layer, also extending in the same direction.
| |
| − | * The second metallization layer surrounds a second channel layer.
| |
| − | * Notably, the first metallization layer has a protruding portion that extends towards the second metallization layer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.
| |
| | | | |
| | ===MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 17804095. MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract|17804095]])=== | | ===MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 17804095. MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract|17804095]])=== |
| Line 388: |
Line 152: |
| | Wei-Chih WANG | | Wei-Chih WANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory structure that includes various layers and a contact. The contact has three portions that extend into different layers. The bottom surface of the first contact portion is lower than the top surface of the source/drain region. The second contact portion is located between the first and third contact portions. The distance between the sidewalls of the first contact portion and the source/drain region is a specific percentage of the width of the source/drain region.
| |
| − |
| |
| − | * Memory structure with a unique contact design
| |
| − | * Contact has three portions extending into different layers
| |
| − | * First contact portion is lower than the source/drain region
| |
| − | * Second contact portion is between the first and third contact portions
| |
| − | * Specific distance between sidewalls of the first contact portion and the source/drain region
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory structure of the present disclosure includes a source/drain region on a substrate, a first dielectric layer covering the source/drain region, a second dielectric layer on the first dielectric layer, and a contact contacting the source/drain region. The contact includes a first contact portion extending into the source/drain region, a second contact portion extending into the first dielectric layer, and a third contact portion extending into the second dielectric layer. A bottom surface of the first contact portion is lower than a top surface of the source/drain region. The second contact portion is between the first contact portion and the third contact portion. A distance between a sidewall of the first contact portion and a sidewall of the source/drain region is 30% to 60% of a width of the source/drain region.
| |
| | | | |
| | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825252. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE simplified abstract|17825252]])=== | | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825252. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE simplified abstract|17825252]])=== |
| Line 408: |
Line 160: |
| | YIN-FA CHEN | | YIN-FA CHEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method of manufacturing a semiconductor device.
| |
| − | * The method involves creating a substrate with two islands, one larger than the other.
| |
| − | * An insulative layer is then deposited to cover the substrate.
| |
| − | * A storage node contact and a conductive feature are formed, with the storage node contact in contact with the smaller island and the conductive feature in contact with the larger island.
| |
| − | * Finally, a conductive line is formed on the insulative layer and connected to the conductive feature.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a method of manufacturing a semiconductor device. The method includes steps of forming a substrate comprising a first island and a second island, wherein the first island has a first area, and the second island has a second area greater than the first area; depositing an insulative layer to cover the substrate; forming a storage node contact and a conductive feature penetrating through the insulative layer, wherein the storage node contact is in contact with the first island and the conductive feature is in contact with the second island; and forming a conductive line on the insulative layer and connected to the conductive feature.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE ([[US Patent Application 17825058. SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE simplified abstract|17825058]])=== | | ===SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE ([[US Patent Application 17825058. SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE simplified abstract|17825058]])=== |
| Line 425: |
Line 167: |
| | | | |
| | YIN-FA CHEN | | YIN-FA CHEN |
| − |
| |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device with a programmable feature.
| |
| − | * The device includes a substrate, a conductive line, a conductive feature, and multiple memory cells.
| |
| − | * The substrate has two islands separated by an isolation structure.
| |
| − | * The first island is smaller in size than the second island.
| |
| − | * The conductive line is placed over the substrate.
| |
| − | * The conductive feature connects the conductive line to the second island.
| |
| − | * The memory cells are located in or on the first island.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present application provides a semiconductor device with a programmable feature. The semiconductor device includes a substrate, a conductive line, a conductive feature and a plurality of memory cells. The substrate includes a first island, a second island and an isolation structure, wherein the isolation structure is disposed between the first island and the second island. The first island has a first area, and the second island has a second area greater than the first area. The conductive line is disposed over the substrate. The conductive feature connects the conductive line to the second island. The plurality of memory cells are disposed in or on the first island.
| |
