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| − | '''Summary of the patent applications from INTERNATIONAL BUSINESS MACHINES CORPORATION on November 9th, 2023'''
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| − | IBM has recently filed several patents for various technologies. One patent application describes devices and methods for creating modular quantum systems with discreet levels of connectivity. This allows for the creation of quantum computing devices with different levels of connectivity, providing flexibility in designing and scaling these devices. Another patent application describes an electronic structure with a first and second substrate joined together using solder bumps and a downstop, controlling the distance between the substrates. A cryogenic electronics device is also described, which includes a semiconductor chip flip-chip bonded to a substrate, with separate regions for bump bonds and circuit elements. Additionally, a semiconductor device structure with a metallization stack and a bi-layer dielectric cap is described, allowing for the formation of logic and memory areas on the chip.
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| − | IBM has also filed a patent application for a system that generates interactive content at an edge node of an edge network. This system fetches cached altered frames from the network to deliver interactive content to users, and can insert interactive content at hotspots within video frames based on user insights and preferences. Another patent application describes a method for access configuration in hybrid network environments, allowing for the automatic establishment of connectivity between client devices and network resources. IBM has also filed a patent application for a method that automatically detects and processes computer input events with multiple intents, using a parse tree and computer agents to determine the processing of each node. Additionally, a patent application describes a computer technology that combines encryption/decryption keys with additional information to create specialized keys, enhancing the security of encrypted data. Finally, a patent application describes a resistor structure with two layers, an electrically insulating layer and a resistive layer, providing improved thermal conductivity and band gap properties.
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| − | Notable applications:
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| − | * Modular quantum systems with discreet levels of connectivity.
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| − | * Electronic structure with solder bumps and a downstop.
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| − | * Cryogenic electronics device with separate regions for bump bonds and circuit elements.
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| − | * Semiconductor device structure with a metallization stack and a bi-layer dielectric cap.
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| − | * System for generating interactive content at an edge node of an edge network.
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| − | * Method for access configuration in hybrid network environments.
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| − | * Method for automatically detecting and processing computer input events with multiple intents.
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| − | * Computer technology that combines encryption/decryption keys with additional information.
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| − | * Resistor structure with an electrically insulating layer and a resistive layer.
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| | ==Patent applications for INTERNATIONAL BUSINESS MACHINES CORPORATION on November 9th, 2023== | | ==Patent applications for INTERNATIONAL BUSINESS MACHINES CORPORATION on November 9th, 2023== |
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| | Cheng-I Lai | | Cheng-I Lai |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for improving the performance of a self-supervised learning (SSL) speech model through a process called finetuning.
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| − |
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| − | * The method involves using one or more computer processors to obtain an initial subnetwork and pruning mask from a pre-trained SSL speech model.
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| − | * The initial subnetwork is adjusted by zeroing out certain weights specified by the pruning mask.
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| − | * A new subnetwork is then trained from the adjusted subnetwork.
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| − | * To achieve a desired level of sparsity, the method further prunes weights with the lowest magnitude in the new subnetwork, regardless of the network structure.
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| − | * Finally, the finetuned subnetwork is used to classify audio segments.
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| − |
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| − | Overall, this patent application presents a technique for refining a self-supervised learning speech model by iteratively adjusting and pruning the network weights to improve its performance in audio classification tasks.
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| − | '''Abstract'''
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| − | One or more computer processors obtain an initial subnetwork at a target sparsity and an initial pruning mask from a pre-trained self-supervised learning (SSL) speech model. The one or more computer processors finetune the initial subnetwork, comprising: the one or more computer processors zero out one or more masked weights in the initial subnetwork specified by the initial pruning mask; the one or more computer processors train a new subnetwork from the zeroed out subnetwork; the one or more computer processors prune one or more weights of lowest magnitude in the new subnetwork regardless of network structure to satisfy the target sparsity. The one or more computer processors classify an audio segment with the finetuned subnetwork.
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| | ===Ontology Driven Contextual Automated Speech Recognition ([[US Patent Application 17735300. Ontology Driven Contextual Automated Speech Recognition simplified abstract|17735300]])=== | | ===Ontology Driven Contextual Automated Speech Recognition ([[US Patent Application 17735300. Ontology Driven Contextual Automated Speech Recognition simplified abstract|17735300]])=== |
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| | Ashish R. Mittal | | Ashish R. Mittal |
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| − | '''Brief explanation'''
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| − | - The patent application describes an automatic speech recognition (ASR) computing system and methodology.
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| − | - The system uses a context acoustic biasing (CAB) engine to match key terms in historical textual content with concepts in an ontology data structure.
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| − | - This matching process generates a contextual term list data structure that includes concept terms related to the matched key terms.
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| − | - The CAB engine then generates acoustic representations of the concept terms in the contextual term list data structure.
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| − | - These acoustic representations are inputted into an ASR computer model, which processes an input speech signal.
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| − | - The ASR computer model uses the acoustic representations to predict a textual representation of the input speech signal.
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| − | - The predicted textual representation is biased towards the acoustic representations of the concept terms in the contextual term list data structure.
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| − |
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| − | '''Abstract'''
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| − | An automatic speech recognition (ASR) computing system and methodology are provided to predict a textual representation of received input speech data. A context acoustic biasing (CAB) engine of the ASR computing system receives historical textual content and an ontology data structure. The CAB engine matches key terms identified in the historical textual content with concepts present in the ontology data structure to generate a contextual term list data structure comprising the concept terms related to concepts matching the key terms. The CAB engine generates acoustic representations of the concept terms in the contextual term list data structure and inputs them to an ASR computer model of the ASR computing system which processes an input speech signal to generate a predicted textual representation of the input speech signal. The predicted textual representation is biased towards the acoustic representations of the concept terms in the contextual term list data structure.
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| | ===QUANTUM COMPUTING THERMODYNAMIC OBSERVABLES OF A CHEMICAL SYSTEM ([[US Patent Application 18347882. QUANTUM COMPUTING THERMODYNAMIC OBSERVABLES OF A CHEMICAL SYSTEM simplified abstract|18347882]])=== | | ===QUANTUM COMPUTING THERMODYNAMIC OBSERVABLES OF A CHEMICAL SYSTEM ([[US Patent Application 18347882. QUANTUM COMPUTING THERMODYNAMIC OBSERVABLES OF A CHEMICAL SYSTEM simplified abstract|18347882]])=== |
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| | Spencer Troy Stober | | Spencer Troy Stober |
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| − | '''Brief explanation'''
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| − | - The patent application describes techniques for determining thermodynamic observables of a chemical system.
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| − | - The system includes a memory and a processor that can execute computer executable components stored in the memory.
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| − | - One component is a potential energy component that fits a potential energy function to a computed potential energy surface of a molecule.
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| − | - Another component is a vibrational mode component that computes an intramolecular vibrational mode of the molecule based on the potential energy surface.
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| − | - A partition component is also included, which computes a partition function based on the intramolecular vibrational mode.
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| − | '''Abstract'''
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| − | Techniques regarding determining thermodynamic observables of a chemical system are provided. For example, one or more embodiments described herein can include a system, which can comprise a memory that can store computer executable components. The system can also include a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a potential energy component that can fit a potential energy function to a computed potential energy surface of a molecule. The computer executable components can also include a vibrational mode component that can compute an intramolecular vibrational mode of the molecule based on the potential energy surface fitted with the potential energy function. Also, the computer executable components can include a partition component that can compute a partition function based on the intramolecular vibrational mode.
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| | ===LOCAL INTERCONNECT FOR CROSS COUPLING ([[US Patent Application 17662436. LOCAL INTERCONNECT FOR CROSS COUPLING simplified abstract|17662436]])=== | | ===LOCAL INTERCONNECT FOR CROSS COUPLING ([[US Patent Application 17662436. LOCAL INTERCONNECT FOR CROSS COUPLING simplified abstract|17662436]])=== |
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| | Heng Wu | | Heng Wu |
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| − | '''Brief explanation'''
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| − | The patent application describes a transistor structure and a method of manufacturing it. Here are the key points:
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| − | * The transistor structure consists of multiple layers of transistors.
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| − | * There are first and second transistors in the first transistor layer, and corresponding first and second transistors in the second transistor layer.
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| − | * A metal routing layer is present between the first and second transistor layers.
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| − | * A first local interconnect connects the first transistor of the first transistor layer to the metal routing layer.
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| − | * A second local interconnect connects the metal routing layer to the second transistor of the second transistor layer.
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| − | Overall, this patent application introduces a transistor structure with multiple layers and interconnects, providing a more efficient and compact design.
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| − | '''Abstract'''
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| − | Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.
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| | ===TOPOLOGICAL SEMI-METAL INTERCONNECTS ([[US Patent Application 18354331. TOPOLOGICAL SEMI-METAL INTERCONNECTS simplified abstract|18354331]])=== | | ===TOPOLOGICAL SEMI-METAL INTERCONNECTS ([[US Patent Application 18354331. TOPOLOGICAL SEMI-METAL INTERCONNECTS simplified abstract|18354331]])=== |
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| | Ching-Tzu Chen | | Ching-Tzu Chen |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for fabricating an interconnect.
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| − | * The method involves creating a layer of topological semi-metal.
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| − | * The topological semi-metal layer is then patterned to form one or more interconnects.
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| − | * A dielectric layer is formed between the interconnects.
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| − | * A hermetic dielectric cap layer is formed on top of the interconnects and the dielectric layer.
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| − |
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| − | '''Abstract'''
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| − | Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.
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| | ===RESISTOR STRUCTURE IN INTEGRATED CIRCUIT ([[US Patent Application 17662439. RESISTOR STRUCTURE IN INTEGRATED CIRCUIT simplified abstract|17662439]])=== | | ===RESISTOR STRUCTURE IN INTEGRATED CIRCUIT ([[US Patent Application 17662439. RESISTOR STRUCTURE IN INTEGRATED CIRCUIT simplified abstract|17662439]])=== |
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| | HUIMEI ZHOU | | HUIMEI ZHOU |
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| − | '''Brief explanation'''
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| − | The patent application describes a resistor structure that consists of two layers: an electrically insulating layer and a resistive layer.
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| − | * The first layer is made of a material with high thermal conductivity, equal to or greater than 100 W/m/K.
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| − | * The second layer is made of resistive material and is directly adjacent to the first layer.
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| − | * The first layer of electrically insulating material has a band gap equal to or greater than 4 eV.
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| − | * The electrically insulating material can be selected from a group of materials including aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).
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| − |
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| − | '''Abstract'''
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| − | Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).
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| | ===PROVIDING SECURE DATA STORAGE AND MANAGEMENT ([[US Patent Application 17662093. PROVIDING SECURE DATA STORAGE AND MANAGEMENT simplified abstract|17662093]])=== | | ===PROVIDING SECURE DATA STORAGE AND MANAGEMENT ([[US Patent Application 17662093. PROVIDING SECURE DATA STORAGE AND MANAGEMENT simplified abstract|17662093]])=== |
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| | Peng Hui Jiang | | Peng Hui Jiang |
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| − | '''Brief explanation'''
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| − | The patent application describes a computer technology that combines an encryption/decryption key with additional information to create a specialized key, thereby enhancing the security of encrypted data.
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| − |
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| − | * The additional information can include client UUID, FQDN, database hardware information, data physical position on the hard disk, and/or stored data creation date.
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| − | * By combining the basic key with this operational and identifier information, the security of the encrypted data is significantly improved.
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| − | * The technology aims to provide a more robust and secure encryption/decryption process.
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| − | * The specialized key generated through this method ensures that the encrypted data remains protected from unauthorized access.
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| − | * This innovation can be applied to various computer systems and networks that require enhanced data security.
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| − | '''Abstract'''
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| − | Computer technology for combining an encryption / decryption (e/d) key with additional information to obtain a specialized e/d key. The additional information one or more of the following types of additional information: client UUID (universally unique identifier), FQDN (fully qualified domain name), database hardware information, data physical position on the hard disk and/or stored data creation date. By combining the basic key with these kind(s) of operational information and/or software / hardware identifier information, the security of the underlying encrypted data can be meaningfully enhanced.
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| | ===MULTI-AGENT CHATBOT WITH MULTI-INTENT RECOGNITION ([[US Patent Application 17662484. MULTI-AGENT CHATBOT WITH MULTI-INTENT RECOGNITION simplified abstract|17662484]])=== | | ===MULTI-AGENT CHATBOT WITH MULTI-INTENT RECOGNITION ([[US Patent Application 17662484. MULTI-AGENT CHATBOT WITH MULTI-INTENT RECOGNITION simplified abstract|17662484]])=== |
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| | Burak Aksar | | Burak Aksar |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for automatically detecting and processing computer input events with multiple intents.
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| − | * The method involves generating a parse tree that interprets the input event and identifies the intents.
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| − | * Confidence evaluation is performed for the nodes in the parse tree.
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| − | * Computer agents provide scores indicating their ability to process each node.
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| − | * The scores from the computer agents are aggregated to determine a final score for each node.
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| − | * Based on the final score, a node is selected for processing the input event.
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| − |
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| − | '''Abstract'''
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| − | A method for automatically detecting and processing a computer input event comprising one or more intents is provided. The method may include, in response to receiving the computer input event, automatically generating a parse tree comprising nodes including a possible interpretation of the received computer input event and at least one determined intent. The method may further include performing a confidence evaluation for the nodes and receiving one or more first scores from one or more computer agents for a respective node to indicate an ability of a respective computer agent to process the respective node. The method may further include, determining a second score for the respective node by aggregating the one or more first scores from the one or more computer agents for the respective node. The method may further include, based on the determined second score, selecting a node for processing the received computer input event.
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| | ===ACCESS CONFIGURATION IN HYBRID NETWORK ENVIRONMENTS ([[US Patent Application 17662242. ACCESS CONFIGURATION IN HYBRID NETWORK ENVIRONMENTS simplified abstract|17662242]])=== | | ===ACCESS CONFIGURATION IN HYBRID NETWORK ENVIRONMENTS ([[US Patent Application 17662242. ACCESS CONFIGURATION IN HYBRID NETWORK ENVIRONMENTS simplified abstract|17662242]])=== |
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| | Qian Xia Song | | Qian Xia Song |
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| − | '''Brief explanation'''
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| − | The patent application describes a method, systems, and computer program products for access configuration in hybrid network environments.
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| − | * The method involves receiving an access configuration request from a client device in one network environment, which is associated with accessing a network resource in another network environment.
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| − | * The access configuration request includes authentication information related to the client device.
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| − | * The method also involves obtaining authentication information associated with the network resource.
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| − | * The first and second authentication information are used to verify the access configuration request.
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| − | * If the request is verified, the method allows for the automatic establishment of connectivity between the client device and the network resource.
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| − |
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| − | '''Abstract'''
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| − | Method, systems, and computer program products for access configuration in hybrid network environments are disclosed. According to the method, an access configuration request is received from a client device in a first network environment, wherein the access configuration request is associated with an access to a network resource in a second network environment and comprises first authentication information associated with the client device. Further, second authentication information associated with the network resource is obtained. The first and second authentication information is further used to determine whether the access configuration request is verified. If the access configuration request is verified, connectivity between the client device and the network resource can be automatically established.
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| | ===DYNAMICALLY GENERATED INTERACTIVE VIDEO CONTENT ([[US Patent Application 17736348. DYNAMICALLY GENERATED INTERACTIVE VIDEO CONTENT simplified abstract|17736348]])=== | | ===DYNAMICALLY GENERATED INTERACTIVE VIDEO CONTENT ([[US Patent Application 17736348. DYNAMICALLY GENERATED INTERACTIVE VIDEO CONTENT simplified abstract|17736348]])=== |
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| | Praveen Jayachandran | | Praveen Jayachandran |
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| − | '''Brief explanation'''
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| − | This patent application describes a system for generating interactive content at an edge node of an edge network.
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| − | * The system fetches cached altered frames from the edge network to deliver interactive content to users.
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| − | * If cached content is not available or different content is intended for delivery, the edge node identifies hotspots within video frames to insert interactive content.
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| − | * The edge node selects content based on user insights and preferences, as well as preferred interaction types and placements.
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| − | * Video creation services are used to alter the incoming video frames and insert selected content at hotspots.
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| − | * The interaction types are applied to present the content to the user.
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| − |
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| − | '''Abstract'''
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| − | Systems, methods and/or computer program products for dynamically generating interactive content at an edge node of an edge network. For each set of video frames received, altered frames cached by the edge network can be fetched (when available) and reused to deliver interactive content to users. Where cached content is not present or distinctly different content from previously delivered content is intended for delivery to user(s), edge node identifies hotspots within video frames to insert interactive content, defining a timing and location for insertion, selects content consistent with user insights and/or preferences as well as an interaction types and placements known to be preferred by the user requesting the video frames. The edge node uses video creation services to alter the incoming video frames into altered video frames, inserts selected content at corresponding hotspots within the video and applies the interaction types for presenting the content to the user.
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| | ===FABRICATION OF EMBEDDED MEMORY DEVICES UTILIZING A SELF ASSEMBLED MONOLAYER ([[US Patent Application 18351605. FABRICATION OF EMBEDDED MEMORY DEVICES UTILIZING A SELF ASSEMBLED MONOLAYER simplified abstract|18351605]])=== | | ===FABRICATION OF EMBEDDED MEMORY DEVICES UTILIZING A SELF ASSEMBLED MONOLAYER ([[US Patent Application 18351605. FABRICATION OF EMBEDDED MEMORY DEVICES UTILIZING A SELF ASSEMBLED MONOLAYER simplified abstract|18351605]])=== |
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| | Ashim DUTTA | | Ashim DUTTA |
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| − | '''Brief explanation'''
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| − | The patent application describes a semiconductor device structure with a metallization stack and a bi-layer dielectric cap.
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| − | * The structure includes one or more patterned metal layers and at least one memory device.
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| − | * The method for forming the metallization stack involves receiving a structure with a metallization layer and a first dielectric cap layer.
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| − | * The metallization layer has a logic area and a memory area.
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| − | * A memory stack is formed over the first dielectric cap layer, and a self-assembled monolayer is formed over the memory stack.
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| − | * A second dielectric cap layer is formed on the first dielectric cap layer, but not on the self-assembled monolayer.
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| − |
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| − | '''Abstract'''
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| − | A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.
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| | ===ELECTRICAL CONNECTIONS BETWEEN DISSIMILAR MATERIALS AT CRYOGENIC TEMPERATURES ([[US Patent Application 17861151. ELECTRICAL CONNECTIONS BETWEEN DISSIMILAR MATERIALS AT CRYOGENIC TEMPERATURES simplified abstract|17861151]])=== | | ===ELECTRICAL CONNECTIONS BETWEEN DISSIMILAR MATERIALS AT CRYOGENIC TEMPERATURES ([[US Patent Application 17861151. ELECTRICAL CONNECTIONS BETWEEN DISSIMILAR MATERIALS AT CRYOGENIC TEMPERATURES simplified abstract|17861151]])=== |
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| | David Abraham | | David Abraham |
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| − | '''Brief explanation'''
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| − | The abstract describes a cryogenic electronics device that includes a semiconductor chip.
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| − | * The device has a substrate that is flip-chip bonded to the semiconductor chip.
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| − | * A bump region on the semiconductor chip contains a concentration of bump bonds.
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| − | * The semiconductor chip also has a predefined region where a plurality of circuit elements are arranged.
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| − | * The predefined region and the bump region are separate regions on the semiconductor chip.
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| − |
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| − | '''Abstract'''
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| − | A cryogenic electronics device includes a semiconductor chip. A substrate is flip-chip bonded to the semiconductor chip. A plurality of bump bonds are concentrated in a bump region of the semiconductor chip. A plurality of circuit elements are arranged in a predefined region of the semiconductor chip. The predefined region and the bump region are separate regions.
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| | ===DOWNSTOP AND BUMP BONDS FORMATION ON SUBSTRATES ([[US Patent Application 17871887. DOWNSTOP AND BUMP BONDS FORMATION ON SUBSTRATES simplified abstract|17871887]])=== | | ===DOWNSTOP AND BUMP BONDS FORMATION ON SUBSTRATES ([[US Patent Application 17871887. DOWNSTOP AND BUMP BONDS FORMATION ON SUBSTRATES simplified abstract|17871887]])=== |
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| | David Abraham | | David Abraham |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an electronic structure with a first substrate and a second substrate joined together using solder bumps and a downstop.
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| − | * The electronic structure has a first substrate with two regions called under bump metallization (UBM) regions.
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| − | * Solder bumps are deposited onto one of the UBM regions.
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| − | * The second UBM region has a wider, shallower, and more rigid downstop compared to the solder bumps.
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| − | * The second substrate is connected to the first substrate using the solder bumps on the first UBM region.
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| − | * The height of the downstop controls the distance between the first and second substrates or between an object and the substrates.
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| − |
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| − | '''Abstract'''
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| − | An electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps is deposited onto the first UBM region. A downstop formed on the second UBM region is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region. A second substrate is joined to the first substrate by the one or more solder bumps located on the first UBM region, and a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.
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| | ===MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY ([[US Patent Application 17936247. MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY simplified abstract|17936247]])=== | | ===MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY ([[US Patent Application 17936247. MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY simplified abstract|17936247]])=== |
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| | Oliver Dial | | Oliver Dial |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes devices and methods for creating modular quantum systems with discreet levels of connectivity.
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| − | * Quantum computing device with modules containing qubits, buses, and readout structures.
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| − | * Multiple types of couplers (classical, short-range, long-range) used to connect the qubits, buses, and readout structures.
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| − | * Connection from the modules to external classical controllers outside of the cryogenic environment.
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| − | * Enables the creation of modular quantum systems with different levels of connectivity.
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| − | * Provides flexibility in designing and scaling quantum computing devices.
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| − | * Allows for easier integration of classical control systems with quantum modules.
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| − |
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| − | '''Abstract'''
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| − | Devices and methods that facilitate modular quantum systems with discreet levels of connectivity are provided. In various embodiments, a quantum computing device can comprise one or more modules comprising at least qubits, buses, and readout structures; a plurality of couplers, wherein the plurality of couplers comprises at least two couplers selected from a group consisting of: classical couplers, short-range couplers, and long-range couplers, that are adapted for coupling a plurality of the at least qubits, buses, and readout structures; and a connection from the one or more modules to one or more classical controllers external to a cryogenic environment comprising the one or more modules.
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