Category:Zhenming Zhou of San Jose CA (US)
Revision as of 03:22, 26 July 2024 by Wikipatents (talk | contribs) (Updating Category:Zhenming_Zhou_of_San_Jose_CA_(US))
Contents
Zhenming Zhou of San Jose CA (US)
Executive Summary
Zhenming Zhou of San Jose CA (US) is an inventor who has filed 45 patents. Their primary areas of innovation include {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} (16 patents), Sensing or reading circuits; Data output circuits (10 patents), {Circuits or methods to verify correct programming of nonvolatile memory cells} (9 patents), and they have worked with companies such as Micron Technology, Inc. (37 patents), MICRON TECHNOLOGY, INC. (8 patents). Their most frequent collaborators include (25 collaborations), (20 collaborations), (7 collaborations).
Patent Filing Activity
_Monthly_Patent_Applications.png)
Technology Areas
_Top_Technology_Areas.png)
List of Technology Areas
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 16 patents
- G11C16/26 (Sensing or reading circuits; Data output circuits): 10 patents
- G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 9 patents
- G11C16/102 (Programming or data input circuits): 8 patents
- G11C16/08 (Address circuits; Decoders; Word-line control circuits): 8 patents
- G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 6 patents
- G06F3/0655 ({Replication mechanisms}): 6 patents
- G11C16/10 (Programming or data input circuits): 6 patents
- G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 5 patents
- G11C16/3404 ({Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}): 4 patents
- G11C16/0483 ({comprising cells having several storage transistors connected in series}): 4 patents
- G11C29/52 (STATIC STORES (semiconductor memory devices): 4 patents
- G06F3/0629 ({Configuration or reconfiguration of storage systems}): 3 patents
- G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 3 patents
- G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 3 patents
- G06F3/0653 ({Monitoring storage devices or systems}): 3 patents
- G11C16/349 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 3 patents
- G06F3/064 ({Management of blocks}): 2 patents
- G11C16/3495 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 2 patents
- G11C16/30 (Power supply circuits): 2 patents
- G11C29/022 (STATIC STORES (semiconductor memory devices): 2 patents
- G11C16/24 (Bit-line control circuits): 2 patents
- G06F3/0611 ({in relation to response time}): 2 patents
- G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 2 patents
- G11C16/28 (STATIC STORES (semiconductor memory devices): 2 patents
- G11C16/16 (STATIC STORES (semiconductor memory devices): 2 patents
- G06F12/1009 (Address translation): 1 patents
- G11C7/1063 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
- G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/50004 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/783 ({with refresh of replacement cells, e.g. in DRAMs}): 1 patents
- G11C16/32 (Timing circuits): 1 patents
- G11C16/12 (Programming voltage switching circuits): 1 patents
- G06F3/0652 ({Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}): 1 patents
- G11C16/3445 ({Circuits or methods to verify correct erasure of nonvolatile memory cells}): 1 patents
- G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
- G11C11/5628 ({Programming or writing circuits; Data input circuits}): 1 patents
- G11C11/5671 ({using charge trapping in an insulator}): 1 patents
- G11C16/3431 (STATIC STORES (semiconductor memory devices): 1 patents
- G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 1 patents
- G06F11/1489 ({through recovery blocks}): 1 patents
- G06F11/3409 ({for performance assessment}): 1 patents
- G11C16/3418 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C11/40618 (STATIC STORES (semiconductor memory devices): 1 patents
- G06N20/00 (Machine learning): 1 patents
- G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 1 patents
- G11C11/4074 (Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits): 1 patents
- G11C11/4076 (Timing circuits (for regeneration management): 1 patents
Companies
_Top_Companies.png)
List of Companies
- Micron Technology, Inc.: 37 patents
- MICRON TECHNOLOGY, INC.: 8 patents
Collaborators
- Yu-Chung Lien of San Jose CA (US) (25 collaborations)
- Murong Lang of San Jose CA (US) (20 collaborations)
- Ching-Huang Lu of Fremont CA (US) (7 collaborations)
- Li-Te Chang of San Jose CA (US) (5 collaborations)
- Tingjun Xie of Milpitas CA (US) (4 collaborations)
- Christina Papagianni of San Jose CA (US) (4 collaborations)
- Zhongguang Xu of San Jose CA (US) (4 collaborations)
- Jian Huang of Union City CA (US) (4 collaborations)
- Jiangli Zhu of San Jose CA (US) (3 collaborations)
- Peng Zhang of Los Altos CA (US) (3 collaborations)
- Jun Wan of San Jose CA (US) (3 collaborations)
- Nagendra Prasad Ganesh Rao of Folsom CA (US) (3 collaborations)
- Ting Luo of Santa Clara CA (US) (2 collaborations)
- Ronit Roneel Prakash (2 collaborations)
- Tomer Tzvi Eliash of Sunnyvale CA (US) (1 collaborations)
- Fangfang Zhu of San Jose CA (US) (1 collaborations)
- Lei Lin of Fremont CA (US) (1 collaborations)
- Pitamber Shukla of San Jose CA (US) (1 collaborations)
- Zhengang Chen of San Jose CA (US) (1 collaborations)
- Vivek Shivhare of Milpitas CA (US) (1 collaborations)
- Vinh Diep of Hayward CA (US) (1 collaborations)
- Aaron Lee of Sunnyvale CA (US) (1 collaborations)
- Pitamber Shukla of Boise ID (US) (1 collaborations)
- Sead Zildzic of Folsom CA (US) (1 collaborations)
- Joshua Garrison of Folsom CA (US) (1 collaborations)
- Charles Kwong of Redwood City CA (US) (1 collaborations)
- Wei Wang of Fremont CA (US) (1 collaborations)
- Michael G. Miller of Boise ID (US) (1 collaborations)
- Ankit V. Vashi of San Jose CA (US) (1 collaborations)
- Jung Sheng Hoei of Newark CA (US) (1 collaborations)
- Paing Z. Htet of Union City CA (US) (1 collaborations)
- Sead Zildzic, JR. of Folsom CA (US) (1 collaborations)
- Thomas Fiala of Folsom CA (US) (1 collaborations)
- Li-Te Chang of Boise ID (US) (1 collaborations)
- Charles See Yeung Kwong of Redwood City CA (US) (1 collaborations)
- Vamsi Pavan Rayaprolu of Santa Clara CA (US) (1 collaborations)
- Seungjune Jeon of Santa Clara CA (US) (1 collaborations)
Subcategories
This category has the following 3 subcategories, out of 3 total.
M
Y
Z
Pages in category "Zhenming Zhou of San Jose CA (US)"
The following 73 pages are in this category, out of 73 total.
1
- 17819826. DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION simplified abstract (Micron Technology, Inc.)
- 17823191. PARTIAL BLOCK READ VOLTAGE OFFSET simplified abstract (Micron Technology, Inc.)
- 17830625. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract (Micron Technology, Inc.)
- 17830802. DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17842278. ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 17858731. ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION simplified abstract (Micron Technology, Inc.)
- 17874828. RELIABILITY BASED DATA VERIFICATION simplified abstract (Micron Technology, Inc.)
- 17876346. MEMORY CELL VOLTAGE LEVEL SELECTION simplified abstract (Micron Technology, Inc.)
- 17887244. VOLTAGE WINDOW ADJUSTMENT simplified abstract (Micron Technology, Inc.)
- 17887348. INDEPENDENT SENSING TIMES simplified abstract (Micron Technology, Inc.)
- 17888080. ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888171. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888225. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17894528. ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17897183. PROXIMITY BASED PARITY DATA MANAGEMENT simplified abstract (Micron Technology, Inc.)
- 17897184. PADDING IN FLASH MEMORY BLOCKS simplified abstract (Micron Technology, Inc.)
- 17898043. NAND DETECT EMPTY PAGE SCAN simplified abstract (Micron Technology, Inc.)
- 17938153. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 17938307. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 17942977. READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18205083. MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18388342. MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS simplified abstract (Micron Technology, Inc.)
- 18388506. READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract (Micron Technology, Inc.)
- 18402306. MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18405049. ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18406687. DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract (Micron Technology, Inc.)
- 18406852. PROGRAM PULSE MODIFICATION simplified abstract (Micron Technology, Inc.)
- 18425383. SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM simplified abstract (Micron Technology, Inc.)
- 18434616. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract (Micron Technology, Inc.)
- 18439318. DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract (Micron Technology, Inc.)
- 18514926. OPTIMIZING DATA RELIABILITY USING ERASE RETENTION simplified abstract (Micron Technology, Inc.)
- 18519248. DYNAMIC READ CALIBRATION simplified abstract (Micron Technology, Inc.)
- 18521458. RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract (Micron Technology, Inc.)
- 18610770. APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 18617430. EMPTY PAGE SCAN OPERATIONS ADJUSTMENT simplified abstract (Micron Technology, Inc.)
- 18663978. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18666063. PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract (Micron Technology, Inc.)
- 18671855. ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR WORDLINES AT CORNER TEMPERATURES IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18672640. ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
M
- Micron technology, inc. (20240176496). OPTIMIZING DATA RELIABILITY USING ERASE RETENTION simplified abstract
- Micron technology, inc. (20240176508). RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract
- Micron technology, inc. (20240177781). READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract
- Micron technology, inc. (20240177795). DYNAMIC READ CALIBRATION simplified abstract
- Micron technology, inc. (20240185924). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185931). PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185934). PROGRAM VERIFY COMPENSATION BY SENSING TIME MODULATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185935). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240203502). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203503). PROGRAM VERIFY LEVEL ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203504). SENSING TIME ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203513). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240231641). MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240231644). APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract
- Micron technology, inc. (20240231666). EMPTY PAGE SCAN OPERATIONS ADJUSTMENT simplified abstract
- Micron technology, inc. (20240233843). SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM simplified abstract
- Micron technology, inc. (20240241664). ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract
- Micron technology, inc. (20240248612). PROGRAM PULSE MODIFICATION simplified abstract
- Micron technology, inc. (20240248619). DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract
- Micron technology, inc. (20240249772). ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240256155). MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE simplified abstract
- Micron technology, inc. (20240256444). GENERATING VIRTUAL BLOCKS USING PARTIAL GOOD BLOCKS simplified abstract
- Micron technology, inc. (20240281145). DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract
- Micron technology, inc. (20240290404). GATE VOLTAGE STEP AND PROGRAM VERIFY LEVEL ADJUSTMENT IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240302967). ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract
- Micron technology, inc. (20240304256). PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract
- Micron technology, inc. (20240311042). ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR WORDLINES AT CORNER TEMPERATURES IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240311311). ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract
U
- US Patent Application 17752590. ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM simplified abstract
- US Patent Application 17830625. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract
- US Patent Application 17830802. DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES simplified abstract
- US Patent Application 17887244. VOLTAGE WINDOW ADJUSTMENT simplified abstract
- US Patent Application 17938307. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract
Categories:
- Yu-Chung Lien of San Jose CA (US)
- Murong Lang of San Jose CA (US)
- Ching-Huang Lu of Fremont CA (US)
- Li-Te Chang of San Jose CA (US)
- Tingjun Xie of Milpitas CA (US)
- Christina Papagianni of San Jose CA (US)
- Zhongguang Xu of San Jose CA (US)
- Jian Huang of Union City CA (US)
- Jiangli Zhu of San Jose CA (US)
- Peng Zhang of Los Altos CA (US)
- Jun Wan of San Jose CA (US)
- Nagendra Prasad Ganesh Rao of Folsom CA (US)
- Ting Luo of Santa Clara CA (US)
- Ronit Roneel Prakash
- Tomer Tzvi Eliash of Sunnyvale CA (US)
- Fangfang Zhu of San Jose CA (US)
- Lei Lin of Fremont CA (US)
- Pitamber Shukla of San Jose CA (US)
- Zhengang Chen of San Jose CA (US)
- Vivek Shivhare of Milpitas CA (US)
- Vinh Diep of Hayward CA (US)
- Aaron Lee of Sunnyvale CA (US)
- Pitamber Shukla of Boise ID (US)
- Sead Zildzic of Folsom CA (US)
- Joshua Garrison of Folsom CA (US)
- Charles Kwong of Redwood City CA (US)
- Wei Wang of Fremont CA (US)
- Michael G. Miller of Boise ID (US)
- Ankit V. Vashi of San Jose CA (US)
- Jung Sheng Hoei of Newark CA (US)
- Paing Z. Htet of Union City CA (US)
- Sead Zildzic, JR. of Folsom CA (US)
- Thomas Fiala of Folsom CA (US)
- Li-Te Chang of Boise ID (US)
- Charles See Yeung Kwong of Redwood City CA (US)
- Vamsi Pavan Rayaprolu of Santa Clara CA (US)
- Seungjune Jeon of Santa Clara CA (US)
- Zhenming Zhou of San Jose CA (US)
- Inventors
- Inventors filing patents with Micron Technology, Inc.
- Inventors filing patents with MICRON TECHNOLOGY, INC.
