Micron technology, inc. (20250087277). ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
Organization Name
Inventor(s)
Yu-Chung Lien of San Jose CA (US)
Zhenming Zhou of San Jose CA (US)
ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
This abstract first appeared for US patent application 20250087277 titled 'ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
Original Abstract Submitted
in some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. the memory device may determine that the portion of the memory is associated with a reliability risk. the memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.
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