Category:Yu-Chung Lien of San Jose CA (US)
Yu-Chung Lien of San Jose CA (US)
Executive Summary
Yu-Chung Lien of San Jose CA (US) is an inventor who has filed 13 patents. Their primary areas of innovation include {comprising cells having several storage transistors connected in series} (5 patents), Sensing or reading circuits; Data output circuits (4 patents), Programming or data input circuits (4 patents), and they have worked with companies such as Micron Technology, Inc. (11 patents), MICRON TECHNOLOGY, INC. (2 patents). Their most frequent collaborators include (12 collaborations), (2 collaborations), (2 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G11C16/0483 ({comprising cells having several storage transistors connected in series}): 5 patents
- G11C16/26 (Sensing or reading circuits; Data output circuits): 4 patents
- G11C16/102 (Programming or data input circuits): 4 patents
- G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 3 patents
- G11C16/32 (Timing circuits): 3 patents
- G11C16/08 (Address circuits; Decoders; Word-line control circuits): 3 patents
- G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 3 patents
- G11C16/349 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 3 patents
- G11C29/52 (STATIC STORES (semiconductor memory devices): 2 patents
- G06F3/0673 ({Single storage device}): 2 patents
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 2 patents
- G11C16/10 (Programming or data input circuits): 2 patents
- G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 2 patents
- G01R19/165 (Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values): 1 patents
- G06F3/064 ({Management of blocks}): 1 patents
- G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
- G06F11/0769 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
- G11C29/08 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/50004 (STATIC STORES (semiconductor memory devices): 1 patents
- G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 1 patents
- G11C16/12 (Programming voltage switching circuits): 1 patents
- G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 1 patents
- G06F3/0653 ({Monitoring storage devices or systems}): 1 patents
- G11C11/5642 ({Sensing or reading circuits; Data output circuits}): 1 patents
- G11C16/24 (Bit-line control circuits): 1 patents
- G11C16/3431 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C16/3404 ({Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}): 1 patents
- G11C16/3418 (STATIC STORES (semiconductor memory devices): 1 patents
Companies
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List of Companies
- Micron Technology, Inc.: 11 patents
- MICRON TECHNOLOGY, INC.: 2 patents
Collaborators
- Zhenming Zhou of San Jose CA (US) (12 collaborations)
- Jun Wan of San Jose CA (US) (2 collaborations)
- Tomer Tzvi Eliash of Sunnyvale CA (US) (2 collaborations)
- Daniel Zhang of Milpitas CA (US) (1 collaborations)
- Peng Zhang of Los Altos CA (US) (1 collaborations)
- Murong Lang of San Jose CA (US) (1 collaborations)
- Shyam Sunder Raghunathan (1 collaborations)
- Tingjun Xie of Milpitas CA (US) (1 collaborations)
- Aaron Lee of Sunnyvale CA (US) (1 collaborations)
- Huai-Yuan Tseng of San Ramon CA (US) (1 collaborations)
- John Paul Aglubat of Meridian ID (US) (1 collaborations)
- Ching-Huang Lu of Fremont CA (US) (1 collaborations)
- Ting Luo of Santa Clara CA (US) (1 collaborations)
Subcategories
This category has the following 3 subcategories, out of 3 total.
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Y
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Pages in category "Yu-Chung Lien of San Jose CA (US)"
The following 56 pages are in this category, out of 56 total.
1
- 17819826. DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION simplified abstract (Micron Technology, Inc.)
- 17830802. DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17874828. RELIABILITY BASED DATA VERIFICATION simplified abstract (Micron Technology, Inc.)
- 17887348. INDEPENDENT SENSING TIMES simplified abstract (Micron Technology, Inc.)
- 17888080. ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888171. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888225. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17894528. ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17897183. PROXIMITY BASED PARITY DATA MANAGEMENT simplified abstract (Micron Technology, Inc.)
- 17897184. PADDING IN FLASH MEMORY BLOCKS simplified abstract (Micron Technology, Inc.)
- 18388506. READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract (Micron Technology, Inc.)
- 18402306. MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18405049. ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18406687. DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract (Micron Technology, Inc.)
- 18439318. DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract (Micron Technology, Inc.)
- 18521458. RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract (Micron Technology, Inc.)
- 18524721. MANAGING ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 18663978. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18666063. PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract (Micron Technology, Inc.)
- 18757422. SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINES (Micron Technology, Inc.)
- 18771479. ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENT (Micron Technology, Inc.)
- 18774642. ENHANCING READ WINDOW BUDGET USING READ VERIFY (Micron Technology, Inc.)
- 18779926. MANAGING AN ORDER OF PROGRAMMING OPERATIONS IN A MEMORY SUB-SYSTEM (Micron Technology, Inc.)
- 18784022. ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES (Micron Technology, Inc.)
- 18784133. RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME (Micron Technology, Inc.)
- 18820480. DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION (Micron Technology, Inc.)
- 18821484. PROXIMITY BASED PARITY DATA MANAGEMENT (Micron Technology, Inc.)
M
- Micron technology, inc. (20240176508). RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract
- Micron technology, inc. (20240177781). READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract
- Micron technology, inc. (20240185924). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185931). PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185934). PROGRAM VERIFY COMPENSATION BY SENSING TIME MODULATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185935). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240194279). MANAGING ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203502). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203503). PROGRAM VERIFY LEVEL ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203504). SENSING TIME ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203507). MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240203513). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240231641). MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240248619). DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract
- Micron technology, inc. (20240249772). ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240256155). MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE simplified abstract
- Micron technology, inc. (20240281145). DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract
- Micron technology, inc. (20240302967). ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract
- Micron technology, inc. (20240304256). PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract
- Micron technology, inc. (20240411449). MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20240419543). PROXIMITY BASED PARITY DATA MANAGEMENT
- Micron technology, inc. (20240420783). DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION
- Micron technology, inc. (20250069675). ENHANCING READ WINDOW BUDGET USING READ VERIFY
- Micron technology, inc. (20250085863). MANAGING AN ORDER OF PROGRAMMING OPERATIONS IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20250086282). RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME
- Micron technology, inc. (20250087277). ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
- Micron technology, inc. (20250087283). ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENT
Categories:
- Zhenming Zhou of San Jose CA (US)
- Jun Wan of San Jose CA (US)
- Tomer Tzvi Eliash of Sunnyvale CA (US)
- Daniel Zhang of Milpitas CA (US)
- Peng Zhang of Los Altos CA (US)
- Murong Lang of San Jose CA (US)
- Shyam Sunder Raghunathan
- Tingjun Xie of Milpitas CA (US)
- Aaron Lee of Sunnyvale CA (US)
- Huai-Yuan Tseng of San Ramon CA (US)
- John Paul Aglubat of Meridian ID (US)
- Ching-Huang Lu of Fremont CA (US)
- Ting Luo of Santa Clara CA (US)
- Yu-Chung Lien of San Jose CA (US)
- Inventors
- Inventors filing patents with Micron Technology, Inc.
- Inventors filing patents with MICRON TECHNOLOGY, INC.