Jing Cheng Lin

Jing Cheng Lin from Suwon-si KR has applied for patents in technology areas such as [[:Category:Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate )}|Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate )}]] with Samsung Electronics Co., Ltd..

Patents

• SEMICONDUCTOR PACKAGE INCLUDING CONDUCTIVE POST AND METHOD OF MANUFACTURING THE SAME (20250174541)

[[Category:Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate )}]]