SEMICONDUCTOR PACKAGE

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Inventor(s)

SEMICONDUCTOR PACKAGE

This abstract first appeared for US patent application 20250006618 titled 'SEMICONDUCTOR PACKAGE

Original Abstract Submitted

provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.