NANYA TECHNOLOGY CORPORATION patent applications published on December 14th, 2023

Patent applications for NANYA TECHNOLOGY CORPORATION on December 14th, 2023

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH COMPOSITE CONTACT STRUCTURE (17835073)

Main Inventor

YU-CHANG CHANG

Brief explanation

The present patent application describes a method for fabricating a semiconductor device. Here are the key points:

• The method involves several steps including forming a first dielectric layer on a substrate, creating an expanded hole in the dielectric layer, and then forming an adhesive layer in the hole using a chemical vapor deposition process.
• Next, a first conductive layer is conformally formed on the adhesive layer using another chemical vapor deposition process.
• Finally, a first conductive structure is formed on the first conductive layer using a third chemical vapor deposition process.
• The adhesive layer, first conductive layer, and first conductive structure together create a composite contact structure.
• The second chemical vapor deposition process for forming the first conductive layer includes an initial deposition step followed by repeated deposition cycles until the desired thickness is achieved.

Potential applications of this technology:

• This method can be used in the fabrication of various semiconductor devices, such as integrated circuits, transistors, and memory devices.
• It can be applied in the manufacturing of electronic devices, including smartphones, computers, and other consumer electronics.

Problems solved by this technology:

• The method provides a reliable and efficient way to create a composite contact structure in a semiconductor device.
• It ensures good adhesion between the different layers, improving the overall performance and reliability of the device.

Benefits of this technology:

• The method allows for precise control over the thickness of the first conductive layer, ensuring optimal performance of the semiconductor device.
• It simplifies the fabrication process by using chemical vapor deposition, which is a widely used and well-established technique in the semiconductor industry.
• The composite contact structure created by this method provides improved electrical conductivity and stability.

Abstract

The present application discloses a method for fabricating a semiconductor device. The method includes forming a first dielectric layer on a substrate; forming an expanded hole in the first dielectric layer; conformally forming an adhesive layer in the expanded hole by a first chemical vapor deposition process; conformally forming a first conductive layer on the adhesive layer by a second chemical vapor deposition process; and forming a first conductive structure on the first conductive layer by a third chemical vapor deposition process. The adhesive layer, the first conductive layer, and the first conductive structure together configure a composite contact structure. The second chemical vapor deposition process includes an initial deposition step and subsequent deposition cycles repeated until the first conductive layer is formed to a predetermined thickness

SEMICONDUCTOR DEVICE WITH GRATING STRUCTURE (17837051)

Main Inventor

CHUN-YEN WEI

Brief explanation

The present application describes a semiconductor device with a grating structure. The device includes two targets, each positioned on a different layer and consisting of a series of equally spaced line features. The first target generates an interference pattern when illuminated by a lens with a grating, and the second target does the same.

• The semiconductor device has a grating structure.
• It includes two targets positioned on different layers.
• Each target consists of equally spaced line features.
• The first target generates an interference pattern when illuminated by a lens with a grating.
• The second target also generates an interference pattern when illuminated by the same lens.

Potential Applications

This technology could have various applications in the field of semiconductor devices and optics. Some potential applications include:

• Optical sensors
• Interferometers
• Metrology systems
• Optical communication devices

Problems Solved

The semiconductor device with a grating structure solves several problems in the field of optics and semiconductor technology. These include:

• Generating interference patterns for precise measurements and analysis.
• Improving the accuracy and sensitivity of optical sensors.
• Enhancing the performance of interferometers and metrology systems.
• Enabling efficient optical communication devices.

Benefits

The semiconductor device with a grating structure offers several benefits, including:

• Increased precision and accuracy in measurements and analysis.
• Improved sensitivity and reliability of optical sensors.
• Enhanced performance and functionality of interferometers and metrology systems.
• Efficient and reliable optical communication.

Abstract

The present application discloses a semiconductor device with a grating structure. The semiconductor device includes a first target positioned on a first layer and including a plurality of line features spaced equally apart from each other according to a first pitch; and a second target positioned on a second layer and including a plurality of line features spaced equally apart from each other according to a second pitch. The first layer is different from the second layer. The first target and the second target do not overlap with each other. The first target is configured to generate an interference pattern when being illuminated by a lens including a grating configured thereon. The second target is configured to generate an interference pattern when being illuminated by the lens including the grating configured thereon.

METHOD AND SYSTEM FOR OVERLAY MEASUREMENT (17837712)

Main Inventor

CHUN-YEN WEI

Brief explanation

The present application describes a method for overlay measurement in which a first target is formed on one layer and a second target is formed on a different layer. These targets are not overlapped with each other. A lens with a grating is positioned to completely overlap with both targets, generating interference patterns. The overlay between the first and second targets is determined through these interference patterns.

• The method involves forming targets on different layers and using a lens with a grating to measure their overlay.
• The targets are not overlapped, ensuring accurate measurement of their alignment.
• Interference patterns generated by the lens and targets are used to determine the overlay between the layers.

Potential Applications

This technology can be applied in various industries and processes where precise alignment and overlay measurement is crucial. Some potential applications include:

• Semiconductor manufacturing: Ensuring accurate alignment of multiple layers in the fabrication process.
• Display panel production: Measuring the alignment of different layers in the production of LCD or OLED panels.
• Microelectronics assembly: Verifying the alignment of components and layers in the assembly of microelectronic devices.

Problems Solved

The method described in this patent application solves the problem of accurately measuring the overlay between different layers. By using targets on separate layers and a lens with a grating, the interference patterns provide a reliable and precise measurement of the overlay. This eliminates the need for complex and time-consuming measurement techniques.

Benefits

The use of this method offers several benefits:

• Accurate measurement: The interference patterns generated by the lens and targets provide a highly accurate measurement of the overlay between layers.
• Simplified process: The method simplifies the overlay measurement process by using targets on separate layers and a lens with a grating, eliminating the need for complex measurement techniques.
• Time and cost savings: The simplified process reduces the time and cost associated with overlay measurement, improving overall efficiency in various industries.

Abstract

The present application discloses present disclosure provides a method for overlay measurement. The method includes forming a first target on a first layer; forming a second target on a second layer different from the first layer, wherein the first target and the second target are not overlapped to each other; positioning a lens including a grating configured thereon at a first location to completely overlap with the first target and the second target to generate an interference pattern of the first target and an interference pattern of the second target; and determining an overlay between the first target and the second target through the interference pattern of the first target and the interference pattern of the second target.

SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE (17838448)

Main Inventor

HSIH-YANG CHIU

Brief explanation

The present application describes a semiconductor device that includes various components such as a substrate, insulative films, electrodes, impurity regions, and a capping layer.

• The device consists of a substrate, which serves as the foundation for the other components.
• A first insulative film is placed on top of the substrate.
• Surrounding the first insulative film is a second insulative film, which partially encloses it.
• A first electrode is positioned on the first insulative film, and it is covered by a capping layer.
• A second electrode is located above the second insulative film and covers the capping layer.
• The substrate contains a plurality of first and second impurity regions.
• The first impurity regions extend beneath and across both the second electrode and the first electrode.
• The second impurity regions are exposed through the second insulative film and the second electrode.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices such as smartphones, computers, and tablets.
• It can be utilized in power management systems, integrated circuits, and memory devices.
• The device can also find applications in sensors, communication devices, and automotive electronics.

Problems solved by this technology:

• The semiconductor device provides improved electrical conductivity and insulation due to the presence of insulative films and impurity regions.
• It allows for efficient power management and signal transmission within electronic devices.
• The device helps in reducing signal interference and noise, resulting in enhanced performance and reliability.

Benefits of this technology:

• The semiconductor device offers a compact and efficient design, making it suitable for miniaturized electronic devices.
• It provides improved electrical performance, leading to faster data processing and higher efficiency.
• The device offers better protection against external factors such as moisture, dust, and physical damage, ensuring longevity and durability.

Abstract

The present application provides a semiconductor device. The semiconductor device includes a substrate, a first insulative film, a second insulative film, a first electrode, a second electrode, a capping layer, a plurality of first impurity regions and a plurality of second impurity regions. The first insulative film is disposed on the substrate. The second insulative film at least partially surrounds the first insulative film. The first electrode and the capping layer, covering the first electrode, are disposed on the first insulative film. The second electrode is disposed over the second insulative film and covers the capping layer. The first and second impurity regions are disposed in the substrate. Each of the first impurity regions extends under and across the second electrode and the first electrode. The second impurity regions are exposed through the second insulative film and the second electrode.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE (17838726)

Main Inventor

HSIH-YANG CHIU

Brief explanation

The present application describes a method for fabricating a semiconductor device. The method involves several steps, including the formation of insulative films, the implantation of dopants, and the deposition of capping layers. The key steps are as follows:

• Forming a first insulative film on a substrate
• Forming a first electrode on the first insulative film
• Implanting dopants in the substrate to create first impurity regions on either side of the first electrode
• Depositing a capping layer to cover the first electrode
• Forming a second insulative film on exposed portions of the substrate
• Forming a second electrode over the capping layer and portions of the second insulative film
• Removing portions of the second insulative film on either side of the second electrode
• Implanting dopants in exposed portions of the substrate to create second impurity regions

Potential applications of this technology:

• Semiconductor devices, such as transistors, diodes, or integrated circuits, can benefit from this fabrication method.
• The method can be used in the production of various electronic devices, including smartphones, computers, and televisions.

Problems solved by this technology:

• The method provides a reliable and efficient way to fabricate semiconductor devices.
• It allows for precise control of impurity regions, which is crucial for the performance and functionality of the devices.

Benefits of this technology:

• The method offers improved performance and functionality of semiconductor devices.
• It enables the production of devices with higher integration density and smaller form factors.
• The fabrication process is more cost-effective and time-efficient compared to traditional methods.

Abstract

The present application provides a method of fabricating a semiconductor device. The method includes steps of forming a first insulative film on a substrate; forming a first electrode on the first insulative film; implanting dopants in the substrate to form a plurality of first impurity regions on either side of the first electrode; depositing a capping layer to cover the first electrode; forming a second insulative film on portions of the substrate exposed through the first electrode and the capping layer; forming a second electrode disposed over the capping layer and portions of the second insulative film; removing portions of the second insulative film on either side of the second electrode; and implanting dopants in portions of the substrate exposed by the second insulative film to form a plurality of second impurity regions.

METHOD OF FABRICATING VOID-FREE CONDUCTIVE FEATURE OF SEMICONDUCTOR DEVICE (17837048)

Main Inventor

CHENG-YAN JI

Brief explanation

The present application describes a method for creating a conductive feature on a substrate. The method involves the following steps:

1. Deposit an insulative layer on the substrate. 2. Form a trench in the insulative layer. 3. Perform a cyclic process consisting of a deposition step and a removal step. 4. Repeat the cyclic process a specific number of times. 5. Fill the trench with the conductive material after the cyclic process.

• The method involves depositing a conductive material in a trench to create a conductive feature.
• The cyclic process ensures the proper deposition and removal of the conductive material.
• The number of times the cyclic process is repeated is predetermined.
• The method allows for precise control over the fabrication of the conductive feature.

Potential Applications

• This method can be used in the fabrication of electronic devices, such as integrated circuits and microchips.
• It can also be applied in the production of sensors, actuators, and other electronic components.
• The method may find use in the development of advanced materials and nanotechnology.

Problems Solved

• The method provides a reliable and controlled way to create a conductive feature on a substrate.
• It eliminates the need for complex and time-consuming fabrication processes.
• The method ensures the uniformity and accuracy of the conductive feature.

Benefits

• The method allows for the efficient and cost-effective production of conductive features.
• It enables the creation of high-quality and precise conductive structures.
• The method can be easily integrated into existing fabrication processes.

Abstract

The present application provides a method of fabricating a conductive feature. The method of fabricating the conductive feature includes steps of depositing an insulative layer on a substrate, forming a trench in the insulative layer, performing a cyclic process comprising a sequence of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step has been performed is equal to a first preset number of times and a number of the times the removal step has been performed is equal to a second preset number of times, and filling the trench with the conductive material after the cyclic process.

METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH FLUORINE-CATCHING LAYER (17746737)

Main Inventor

KUO-HUI SU

Brief explanation

The present disclosure describes a method for preparing a semiconductor device structure with a fluorine-catching layer. The method involves several steps, including:

• Forming a first dielectric layer over a semiconductor substrate.
• Creating a first conductive via structure in the first dielectric layer.
• Applying a second dielectric layer over the first dielectric layer to cover the first conductive via structure.
• Depositing a fluorine-catching layer over the second dielectric layer.
• Forming a third dielectric layer over the fluorine-catching layer.
• Creating a second conductive via structure in the third dielectric layer, the fluorine-catching layer, and the second dielectric layer.

Potential applications of this technology include:

• Semiconductor manufacturing: This method can be used in the production of semiconductor devices, such as integrated circuits, to improve their performance and reliability.
• Electronics industry: The semiconductor devices prepared using this method can be used in various electronic devices, such as smartphones, computers, and televisions.

The problems solved by this technology are:

• Fluorine contamination: The fluorine-catching layer helps to prevent fluorine atoms from diffusing into the semiconductor device structure, which can cause device failure or degradation.
• Dielectric layer protection: The fluorine-catching layer acts as a protective barrier for the underlying dielectric layers, preventing damage or degradation during subsequent processing steps.

The benefits of this technology include:

• Enhanced device performance: By preventing fluorine contamination, the semiconductor device structure can maintain its intended electrical properties, leading to improved device performance.
• Increased device reliability: The fluorine-catching layer helps to protect the dielectric layers, reducing the risk of device failure or degradation over time.
• Simplified manufacturing process: The method described in this disclosure can be integrated into existing semiconductor manufacturing processes, minimizing the need for significant process modifications.

Abstract

The present disclosure provides a method for preparing a semiconductor device structure with a fluorine-catching layer. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a first conductive via structure in the first dielectric layer. The method also includes forming a second dielectric layer over the first dielectric layer and covering the first conductive via structure, and forming a fluorine-catching layer over the second dielectric layer. The method further includes forming a third dielectric layer over the fluorine-catching layer, and forming a second conductive via structure in the third dielectric layer, the fluorine-catching layer, and the second dielectric layer.

SEMICONDUCTOR DEVICE WITH FUSE STRUCTURE (17839796)

Main Inventor

HSIH-YANG CHIU

Brief explanation

Abstract:

A semiconductor device is described in this patent application. The device consists of a substrate, a fuse element, and a fuse medium. The fuse element is located within the substrate, while the fuse medium surrounds the lateral surface of the fuse element.

Patent/Innovation Explanation:

• The semiconductor device includes a substrate, which is the base material on which the device is built.
• It also includes a fuse element, which is a component that can be selectively blown or melted to create an open circuit.
• The fuse element is positioned within the substrate, likely embedded or integrated into it.
• The device further comprises a fuse medium, which surrounds the lateral surface of the fuse element.
• The fuse medium likely acts as a protective layer or insulation around the fuse element.

Potential Applications:

• Integrated circuits: The semiconductor device can be used in various integrated circuits, such as microprocessors, memory chips, or sensors.
• Circuit protection: The fuse element and fuse medium can be utilized to protect circuits from overcurrent or short circuits, preventing damage to the device or system.
• Programmable logic devices: The fuse element can be selectively blown to configure or program the device for specific functions or settings.

Problems Solved:

• Circuit protection: The fuse element and fuse medium provide a means to protect circuits from excessive current or short circuits, preventing damage to the device or system.
• Customization and configuration: The fuse element allows for programmability, enabling the device to be customized or configured for specific applications or settings.

Benefits:

• Enhanced circuit protection: The fuse element and fuse medium provide an additional layer of protection against overcurrent or short circuits, improving the reliability and longevity of the device.
• Flexibility and customization: The programmable fuse element allows for customization and configuration of the device, making it adaptable to different applications or settings.
• Space-saving: By integrating the fuse element within the substrate and surrounding it with the fuse medium, the device can be more compact and space-efficient.

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed within the substrate. The fuse medium surrounds a lateral surface of the fuse element.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH FUSE STRUCTURE (17840097)

Main Inventor

HSIH-YANG CHIU

Brief explanation

The abstract describes a method for fabricating a semiconductor device. Here is a simplified explanation of the abstract:

• The method involves three main steps: providing a substrate, forming a fuse element within the substrate, and forming a fuse medium in contact with the fuse element.
• The fuse element is located within the substrate and extends from its upper surface.
• The fuse medium is placed in contact with the fuse element but is spaced apart from the upper surface of the substrate.

Potential Applications

This technology can be applied in various semiconductor devices, including but not limited to:

• Integrated circuits (ICs)
• Microprocessors
• Memory devices
• Power devices

Problems Solved

The method for fabricating a semiconductor device described in the patent application solves several problems, such as:

• Efficiently integrating fuse elements within a substrate.
• Ensuring proper contact between the fuse element and the fuse medium.
• Providing a reliable and accurate fuse mechanism for circuit protection or programming purposes.

Benefits

The use of this method for fabricating a semiconductor device offers several benefits, including:

• Improved reliability and accuracy of fuse mechanisms.
• Enhanced circuit protection and programming capabilities.
• Efficient integration of fuse elements within the substrate.
• Potential cost savings in the manufacturing process.

Abstract

A method for fabricating a semiconductor device is provided. The method includes providing a substrate; forming a fuse element within the substrate and extending from an upper surface of the substrate; and forming a fuse medium in contact with the fuse element, wherein the fuse medium is spaced apart from the upper surface of the substrate.

SEMICONDUCTOR DEVICE WITH COMPOSITE CONTACT STRUCTURE (17834940)

Main Inventor

YU-CHANG CHANG

Brief explanation

The present patent application describes a semiconductor device and a method for fabricating it. The device includes a substrate, a first dielectric layer, a first conductive structure, a first conductive layer, and an adhesive layer. 

• The semiconductor device includes a substrate, which serves as the foundation for the device.
• A first dielectric layer is positioned on the substrate, providing insulation.
• A first conductive structure is positioned in the first dielectric layer and has a bottle-shaped cross-sectional profile, allowing for specific electrical properties.
• A first conductive layer is located between the first conductive structure and the first dielectric layer, as well as between the first conductive structure and the substrate, providing electrical conductivity.
• An adhesive layer is positioned between the first conductive layer and the first dielectric layer, as well as between the first conductive layer and the substrate, ensuring stability and adhesion.

The combination of the adhesive layer, first conductive layer, and first conductive structure creates a composite contact structure with an aspect ratio greater than 7.

Potential Applications

This technology has potential applications in various fields, including:

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit design and fabrication

Problems Solved

The disclosed semiconductor device and fabrication method address several challenges, such as:

• Ensuring proper electrical conductivity and insulation in a semiconductor device
• Achieving a specific cross-sectional profile for improved electrical properties
• Enhancing stability and adhesion between different layers in the device

Benefits

The described technology offers several benefits, including:

• Improved electrical performance due to the specific cross-sectional profile of the conductive structure
• Enhanced stability and adhesion provided by the adhesive layer
• Increased aspect ratio of the composite contact structure, allowing for more efficient electrical connections.

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer positioned on the substrate; a first conductive structure positioned in the first dielectric layer and including a bottle-shaped cross-sectional profile; a first conductive layer positioned between the first conductive structure and the first dielectric layer and between the first conductive structure and the substrate; an adhesive layer positioned between the first conductive layer and the first dielectric layer and between the first conductive layer and the substrate. The adhesive layer, the first conductive layer, and the first conductive structure together configure a composite contact structure. An aspect ratio of the composite contact structure is greater than 7.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING HYBRID BONDING PAD (17840081)

Main Inventor

Yi-Jen LO

Brief explanation

The present disclosure describes a method of manufacturing a semiconductor structure. This method involves several steps, including providing a first semiconductor substrate, forming a first conductive pad over the substrate, and forming a first hybrid bonding pad on top of the conductive pad. The first hybrid bonding pad is made of nano-twins copper and has a thickness that is less than the thickness of the first conductive pad.

• The method involves providing a first semiconductor substrate.
• A first conductive pad is formed over the first semiconductor substrate.
• A first hybrid bonding pad is formed on top of the first conductive pad.
• The first hybrid bonding pad is made of nano-twins copper.
• The thickness of the first hybrid bonding pad is less than the thickness of the first conductive pad.

Potential applications of this technology:

• Manufacturing of semiconductor structures
• Improving the performance and reliability of semiconductor devices

Problems solved by this technology:

• Enhancing the bonding between different layers of a semiconductor structure
• Improving the electrical conductivity of the bonding pad

Benefits of this technology:

• Increased performance and reliability of semiconductor devices
• Enhanced electrical conductivity and bonding strength
• Cost-effective manufacturing process

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a first semiconductor substrate. The method also includes forming a first conductive pad over the first semiconductor substrate. The method further includes forming a first hybrid bonding pad on the first conductive pad, wherein the first hybrid bonding pad includes nano-twins copper, and a thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

SEMICONDUCTOR STRUCTURE HAVING HYBRID BONDING PAD (17839806)

Main Inventor

YI-JEN LO

Brief explanation

The abstract describes a semiconductor structure and a method of manufacturing it. The structure includes a first semiconductor substrate, a first conductive pad, and a first hybrid bonding pad. The first conductive pad is located on top of the first semiconductor substrate, and the first hybrid bonding pad is on top of the first conductive pad. The first hybrid bonding pad is made of nano-twins copper and has a smaller thickness than the first conductive pad.

• The semiconductor structure includes a first semiconductor substrate.
• The structure has a first conductive pad located on top of the first semiconductor substrate.
• A first hybrid bonding pad is present on the first conductive pad.
• The first hybrid bonding pad is made of nano-twins copper.
• The thickness of the first hybrid bonding pad is smaller than the thickness of the first conductive pad.

Potential applications of this technology:

• Semiconductor manufacturing
• Electronics industry
• Integrated circuits

Problems solved by this technology:

• Improved bonding between semiconductor structures
• Enhanced electrical conductivity
• Reduction in thickness for space-saving designs

Benefits of this technology:

• Increased efficiency in semiconductor manufacturing
• Improved performance of electronic devices
• Compact and thinner designs for electronic components

Abstract

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a first semiconductor substrate, a first conductive pad, and a first hybrid bonding pad. The first conductive pad is over the first semiconductor substrate. The first hybrid bonding pad is on the first conductive pad. The first hybrid bonding pad includes nano-twins copper. A thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH SINGLE SIDE CAPACITOR (17748869)

Main Inventor

YU-MIN CHOU

Brief explanation

The present disclosure describes a method for manufacturing a semiconductor structure. The method involves several steps, including the formation of multiple layers over a substrate, the creation of openings to expose landing pads in the substrate, the formation of electrodes in the openings, the removal of sacrificial layers, and the formation of a conductive layer.

• The method begins with the provision of a substrate.
• Multiple layers, including nitride layers and sacrificial layers, are formed over the substrate in a specific sequence.
• Openings are created to expose landing pads in the substrate.
• Electrodes are formed in the openings.
• The sacrificial layers are removed simultaneously.
• A conductive layer is formed, which conforms to the electrodes and the various nitride layers.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit production

Problems solved by this technology:

• Simplifies the manufacturing process of semiconductor structures
• Provides a method for forming electrodes and a conductive layer in a precise and efficient manner

Benefits of this technology:

• Improved manufacturing efficiency
• Enhanced precision in the formation of electrodes and conductive layers
• Simplified manufacturing process for semiconductor structures

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.

CAPACITOR STRUCTURE AND METHOD FOR FABRICATING THE SAME (17836579)

Main Inventor

DA-ZEN CHUANG

Brief explanation

The invention is a capacitor structure that includes a U-shaped bottom electrode with a cap dielectric at its open end, a top electrode, and a capacitor dielectric layer between them. This structure forms an outer capacitor around a solid inner capacitor in the shape of a cylinder. The cap dielectric divides the outer and inner capacitors. The inner capacitor and outer capacitor are fabricated separately to prevent damage to the structure during fabrication.

• The capacitor structure includes a U-shaped bottom electrode with a cap dielectric at its open end.
• A top electrode is present in the structure.
• A capacitor dielectric layer is placed between the bottom and top electrodes.
• The structure forms an outer capacitor around a solid inner capacitor in the shape of a cylinder.
• The cap dielectric divides the outer and inner capacitors.
• The inner capacitor and outer capacitor are fabricated separately to prevent damage to the structure during fabrication.

Potential Applications

This technology can be applied in various electronic devices and systems that require capacitors, such as:

• Consumer electronics (smartphones, tablets, laptops)
• Power supply units
• Electric vehicles
• Renewable energy systems (solar panels, wind turbines)
• Industrial machinery and equipment

Problems Solved

The invention addresses the following problems:

• Damage to the structure of the capacitor during fabrication.
• Ensuring the stability and reliability of the capacitor structure.
• Simplifying the fabrication process of capacitors.

Benefits

The benefits of this technology include:

• Enhanced durability and reliability of the capacitor structure.
• Simplified fabrication process.
• Improved performance and efficiency of electronic devices and systems.
• Cost-effectiveness in manufacturing capacitors.

Abstract

This invention provides a capacitor structure includes a U-shaped bottom electrode having a cap dielectric provided at its open end, a top electrode and a capacitor dielectric layer interposed between the bottom electrode and the top electrode to constitute an outer capacitor around a cylinder type solid inner capacitor, and the outer capacitor and the inner capacitor are divided by the cap dielectric. The cylinder type solid inner capacitor and the outer capacitor are fabricated separately so that the cylinder type solid inner capacitor may support its own weight to prevent its structure from being damaged during the fabrication of the capacitor.

ELECTRICAL OVER STRESS PROTECTION DEVICE (17838282)

Main Inventor

Chang-Ting Wu

Brief explanation

Abstract:

An electrical over stress protection device is described in this patent application. The device includes a detection circuit that is capable of detecting the input voltage from a pad. When the input voltage exceeds a preset voltage, the detection circuit provides a first discharge path. Additionally, the detection circuit provides a turn-on voltage to a discharge protection circuit, which controls the discharge protection circuit to provide at least one second discharge path.

Patent/Innovation Explanation:

• The patent describes an electrical over stress protection device.
• The device includes a detection circuit that detects the input voltage from a pad.
• When the input voltage is higher than a preset voltage, the detection circuit provides a first discharge path.
• The detection circuit also provides a turn-on voltage to a discharge protection circuit.
• The discharge protection circuit is controlled by the turn-on voltage to provide at least one second discharge path.

Potential Applications:

• Electrical over stress protection devices can be used in various electronic systems and devices.
• They can be implemented in power supplies, circuit boards, and integrated circuits to protect against voltage spikes and overloads.
• These devices can be utilized in consumer electronics, automotive systems, industrial equipment, and telecommunications devices.

Problems Solved:

• Electrical over stress can cause damage to electronic components and systems.
• This technology solves the problem of protecting electronic devices from voltage spikes and overloads.
• It provides a mechanism to discharge excess voltage and prevent damage to sensitive components.

Benefits:

• The electrical over stress protection device offers a reliable and efficient solution for protecting electronic systems.
• It helps prevent damage to components, extending the lifespan of electronic devices.
• The device can be easily integrated into existing electronic systems and circuits.
• It provides multiple discharge paths, enhancing the overall protection capability.

Abstract

An electrical over stress protection device is provided. A detection circuit detects an input voltage from a pad, provides a first discharge path when the input voltage is higher than a preset voltage, and provides a turn-on voltage to a discharge protection circuit to control the discharge protection circuit to provide at least one second discharge path.

SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE (17837052)

Main Inventor

PEI-ROU JIANG

Brief explanation

The present disclosure describes a semiconductor structure with a tapered bit line configuration. The structure includes a substrate, a bit line structure with a cylindrical portion and a step portion, a polysilicon layer, and a landing pad.

• The semiconductor structure has a tapered bit line configuration.
• The bit line structure consists of a cylindrical portion and a step portion.
• The polysilicon layer is located over the substrate and surrounds the bit line structure.
• The landing pad is positioned over the polysilicon layer and the step portion.

Potential Applications

This technology can be applied in various semiconductor devices and integrated circuits, including:

• Memory devices
• Logic devices
• Microprocessors
• Storage devices

Problems Solved

The semiconductor structure with a tapered bit line configuration addresses the following issues:

• Improves the performance and efficiency of semiconductor devices.
• Reduces signal interference and noise.
• Enhances the reliability and functionality of integrated circuits.

Benefits

The use of a tapered bit line configuration in the semiconductor structure offers several advantages:

• Increased speed and performance of semiconductor devices.
• Improved signal integrity and reduced noise.
• Enhanced reliability and functionality of integrated circuits.
• Enables higher density and smaller form factor of devices.

Abstract

The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE (17837718)

Main Inventor

PEI-ROU JIANG

Brief explanation

The present disclosure describes a method of manufacturing a semiconductor structure. The method involves several steps including forming a bit line structure, forming a spacer, and forming a polysilicon layer.

• The method begins by providing a substrate.
• A bit line structure is then formed over the substrate.
• A spacer is formed around the bit line structure.
• A polysilicon layer is deposited to cover both the bit line structure and the spacer.
• The polysilicon layer is etched in a first operation to achieve a certain height, which is lower than the height of the bit line structure or the spacer.
• A second etching operation is performed on a portion of the spacer.
• Finally, a third etching operation is carried out on the polysilicon layer to obtain a second height, which is lower than the first height.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Integrated circuit fabrication
• Memory device production

Problems solved by this technology:

• Provides a method for manufacturing a semiconductor structure with precise control over the height of the polysilicon layer
• Enables the formation of a polysilicon layer that is lower than the surrounding structures

Benefits of this technology:

• Improved accuracy and control in the manufacturing process
• Allows for the creation of semiconductor structures with specific height requirements
• Enhances the performance and reliability of the resulting semiconductor devices.

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

SEMICONDUCTOR DEVICE WITH CONDUCTIVE CAP LAYER OVER CONDUCTIVE PLUG AND METHOD FOR PREPARINGING THE SAME (18234029)

Main Inventor

HUNG-CHI TSAI

Brief explanation

The present disclosure describes a semiconductor device that includes various components such as a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer.

• The word lines are placed over the semiconductor substrate.
• The mask layers are positioned over the word lines.
• The spacers are located on the sidewalls of both the word lines and the mask layers.
• A conductive plug is placed between the word lines.
• A conductive cap layer is placed over the conductive plug.
• A dielectric layer is placed over the word lines and spacers.
• Each spacer consists of an inner spacer, an outer spacer, and an air gap.
• The inner spacer is in contact with the respective word line and mask layer.
• An air gap is present between the inner spacer and the outer spacer.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices such as computers, smartphones, and tablets.
• It can be utilized in memory devices, processors, and other integrated circuits.

Problems solved by this technology:

• The described semiconductor device helps in improving the performance and efficiency of electronic devices.
• It addresses the need for smaller and more compact semiconductor components.

Benefits of this technology:

• The use of spacers and air gaps helps in reducing interference and improving signal integrity.
• The conductive cap layer and dielectric layer provide protection and insulation to the underlying components.
• This technology enables the fabrication of smaller and more efficient semiconductor devices.

Abstract

The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.