17837718. METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE simplified abstract (NANYA TECHNOLOGY CORPORATION)

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE

Organization Name

NANYA TECHNOLOGY CORPORATION

Inventor(s)

PEI-ROU Jiang of TAINAN CITY (TW)

CHAO-WEN Lay of NEW TAIPEI CITY (TW)

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17837718 titled 'METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE

Simplified Explanation

The present disclosure describes a method of manufacturing a semiconductor structure. The method involves several steps including forming a bit line structure, forming a spacer, and forming a polysilicon layer.

• The method begins by providing a substrate.
• A bit line structure is then formed over the substrate.
• A spacer is formed around the bit line structure.
• A polysilicon layer is deposited to cover both the bit line structure and the spacer.
• The polysilicon layer is etched in a first operation to achieve a certain height, which is lower than the height of the bit line structure or the spacer.
• A second etching operation is performed on a portion of the spacer.
• Finally, a third etching operation is carried out on the polysilicon layer to obtain a second height, which is lower than the first height.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Integrated circuit fabrication
• Memory device production

Problems solved by this technology:

• Provides a method for manufacturing a semiconductor structure with precise control over the height of the polysilicon layer
• Enables the formation of a polysilicon layer that is lower than the surrounding structures

Benefits of this technology:

• Improved accuracy and control in the manufacturing process
• Allows for the creation of semiconductor structures with specific height requirements
• Enhances the performance and reliability of the resulting semiconductor devices.

Original Abstract Submitted

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.