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Category:G06F12/0811
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Pages in category "G06F12/0811"
The following 37 pages are in this category, out of 37 total.
1
- 17852189. HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY simplified abstract (Intel Corporation)
- 17944031. SYSTEMS AND METHODS FOR ADAPTIVE HYBRID HARDWARE PRE-FETCH simplified abstract (Huawei Technologies Co., Ltd.)
- 17955618. Data Reuse Cache simplified abstract (ADVANCED MICRO DEVICES, INC.)
- 17958120. PUSHED PREFETCHING IN A MEMORY HIERARCHY simplified abstract (ADVANCED MICRO DEVICES, INC.)
- 18054388. Preemption Techniques for Memory-Backed Registers simplified abstract (Apple Inc.)
- 18084540. STORAGE SYSTEM, METHOD, AND APPARATUS FOR FAST IO ON PCIE DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
- 18243809. MULTICORE SHARED CACHE OPERATION ENGINE simplified abstract (Texas Instruments Incorporated)
- 18253174. Controlling Memory Frequency Based on Transaction Queue Occupancy simplified abstract (GOOGLE LLC)
- 18358587. MEMORY SYSTEM simplified abstract (SK hynix Inc.)
- 18451698. Dynamic Cache Resource Allocation for Quality of Service and System Power Reduction simplified abstract (MediaTek Inc.)
- 18463101. SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS simplified abstract (Texas Instruments Incorporated)
- 18482644. Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System simplified abstract (Micron Technology, Inc.)
- 18491474. INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES simplified abstract (Intel Corporation)
- 18508356. CACHE SIZE CHANGE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
- 18516716. SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION simplified abstract (Intel Corporation)
- 18517866. HIGH BANDWIDTH GATHER CACHE simplified abstract (Micron Technology, Inc.)
- 18548198. PHYSICAL MEMORY ADDRESS OMISSION OR OBFUSCATION WITHIN AN EXECUTION TRACE simplified abstract (MICROSOFT TECHNOLOGY LICENSING, LLC)
- 18548318. MEMORY ADDRESS COMPRESSION WITHIN AN EXECUTION TRACE simplified abstract (MICROSOFT TECHNOLOGY LICENSING, LLC)
A
- Advanced micro devices, inc. (20240111674). Data Reuse Cache simplified abstract
- Advanced micro devices, inc. (20240111678). PUSHED PREFETCHING IN A MEMORY HIERARCHY simplified abstract
- ADVANCED MICRO DEVICES, INC. patent applications on April 4th, 2024
- Apple inc. (20240095176). Preemption Techniques for Memory-Backed Registers simplified abstract
- Apple Inc. patent applications on March 21st, 2024
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- US Patent Application 17664722. CACHE MANAGEMENT USING CACHE SCOPE DESIGNATION simplified abstract
- US Patent Application 17736557. HYBRID ALLOCATION OF DATA LINES IN A STREAMING CACHE MEMORY simplified abstract
- US Patent Application 18229814. CONFIGURABLE CACHE FOR COHERENT SYSTEM simplified abstract
- US Patent Application 18361128. BOOT PROCESS FOR EARLY DISPLAY INITIALIZATION AND VISUALIZATION simplified abstract
- US Patent Application 18450079. STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS simplified abstract