18548198. PHYSICAL MEMORY ADDRESS OMISSION OR OBFUSCATION WITHIN AN EXECUTION TRACE simplified abstract (MICROSOFT TECHNOLOGY LICENSING, LLC)

PHYSICAL MEMORY ADDRESS OMISSION OR OBFUSCATION WITHIN AN EXECUTION TRACE

Organization Name

MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor(s)

Jordi Mola of Bellevue WA (US)

PHYSICAL MEMORY ADDRESS OMISSION OR OBFUSCATION WITHIN AN EXECUTION TRACE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18548198 titled 'PHYSICAL MEMORY ADDRESS OMISSION OR OBFUSCATION WITHIN AN EXECUTION TRACE

Simplified Explanation

The patent application abstract describes a method for omitting or obfuscating physical memory addresses within an execution trace by logging virtual memory page mappings in a translation lookaside buffer (TLB) without revealing the actual physical memory addresses.

• The microprocessor logs TLB entries mapping virtual memory pages to physical memory pages without including the physical memory addresses in the execution trace.
• The microprocessor ensures that live TLB entries mapping to the same physical address are logged and indicated in the execution trace without disclosing the actual physical address.

Potential Applications

This technology could be applied in secure computing environments where the visibility of physical memory addresses needs to be restricted to prevent unauthorized access to sensitive information.

Problems Solved

This innovation addresses the issue of exposing physical memory addresses in execution traces, which could potentially lead to security vulnerabilities if accessed by malicious actors.

Benefits

- Enhanced security by obfuscating physical memory addresses in execution traces - Protection of sensitive information stored in memory from unauthorized access

Potential Commercial Applications

A potential commercial application of this technology could be in the development of secure computing systems for industries such as finance, healthcare, and government where data privacy and security are paramount.

Possible Prior Art

One possible prior art in this field is the use of memory encryption techniques to protect sensitive data in memory from unauthorized access. However, the specific method of obfuscating physical memory addresses within an execution trace as described in this patent application may be a novel approach.

How does this technology impact system performance?

The article does not provide information on the potential impact of this technology on system performance. It would be important to understand if there are any performance trade-offs associated with obfuscating physical memory addresses in execution traces.

What are the potential limitations of this technology?

The article does not discuss any limitations or constraints of this technology. It would be valuable to know if there are any specific scenarios or use cases where this method may not be effective or applicable.

Original Abstract Submitted

Omitting or obfuscating physical memory addresses within an execution trace. A microprocessor identifies a first translation lookaside buffer (TLB) entry mapping a first virtual memory page to a physical memory page, and initiates logging of the first TLB entry by initiating logging of at least a first virtual address of the first virtual memory page and a first identifier. The microprocessor identifies a second TLB entry mapping a second virtual memory page to the physical memory page, and initiates logging of the second TLB entry by initiating logging of at least a second virtual address of the second virtual memory page and a second identifier. The microprocessor determines that the first and second TLB entries are each live, logged into the execution trace, and mapped to the same physical address, and ensures that the execution trace indicates that the first and second TLB entries each map to the physical address.