18463101. SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS simplified abstract (Texas Instruments Incorporated)

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SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS

Organization Name

Texas Instruments Incorporated

Inventor(s)

Kai Chirca of Richardson TX (US)

Joseph R. M. Zbiciak of San Jose CA (US)

Matthew D. Pierson of Murphy TX (US)

SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18463101 titled 'SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS

Simplified Explanation

The abstract describes a prefetch unit with multiple memories and a memory controller. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter has address slots and direction prediction fields associated with each address slot. The prefetch buffer has buffer slots with various fields for storing data.

  • The prefetch unit has multiple memories and a memory controller.
  • The memory controller includes a prefetch stream filter and a prefetch buffer.
  • The prefetch stream filter has address slots and direction prediction fields.
  • Each address slot in the prefetch stream filter is associated with a direction prediction field.
  • The prefetch buffer has buffer slots with various fields for storing data.
  • Each buffer slot in the prefetch buffer has an address field, direction prediction field, data pending field, data valid field, and sub-slots for storing data.
  • The address field in each buffer slot stores at least a portion of the corresponding address.

Potential applications of this technology:

  • Computer processors and systems that require efficient memory access.
  • High-performance computing applications that rely on prefetching data.
  • Data-intensive tasks such as machine learning, data analytics, and simulations.

Problems solved by this technology:

  • Improves memory access efficiency by prefetching data.
  • Reduces memory latency by predicting memory access patterns.
  • Optimizes data retrieval and processing in memory-intensive applications.

Benefits of this technology:

  • Faster data access and processing.
  • Improved overall system performance.
  • Enhanced efficiency in memory-intensive tasks.
  • Reduced memory latency and improved responsiveness.


Original Abstract Submitted

A prefetch unit includes multiple memories; and a memory controller coupled to the multiple memories. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots. The prefetch buffer includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.

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