Micron Technology, Inc. patent applications on March 14th, 2024
Patent Applications by Micron Technology, Inc. on March 14th, 2024
Micron Technology, Inc.: 49 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), G06N3/063 (7), G06F3/0679 (7), G11C16/26 (6), H04N5/3745 (6)
With keywords such as: memory, device, data, cells, circuit, array, operations, processing, configured, and include in patent application abstracts.
See the following report for Micron Technology, Inc. patent applications on March 14th, 2024: Micron Technology, Inc. patent applications on March 14th, 2024
Patent Applications by Micron Technology, Inc.
Inventor(s): Mow Yiak Goh of Boise ID (US) for micron technology, inc., Mark Clouse of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems, apparatuses, and methods related to conversion of access data based on memory device size are described herein. an example apparatus can include a memory device, a mode register, an address decoder, and a memory controller. the memory device can include an array of memory cells. the memory controller can cause performance of a memory access. performance of the memory access can include receiving access data associated with a first memory device size to access data stored in the memory device. the memory device can be a second memory device size. performance of the memory access can further include accessing the data in the memory device that is the second memory device size using the access data.
20240086070.READ DISTURB MANAGEMENT FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Francesco Basso of Portici (IT) for micron technology, inc., Francesco Falanga of Quarto (IT) for micron technology, inc., Alberto Sassara of Napoli (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for read disturb management for memory are described. in some instances, data may be read from a first page of a virtual block of a memory system. if the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. the memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). the memory system may then refresh the pages.
Inventor(s): Aswin Thiruvengadam of Folsom CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
Inventor(s): Guang Hu of Mountain View CA (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system comprises a memory device including a plurality of management units and a processing device. the processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
20240086090.MEMORY CHANNEL DISABLEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Yu-Sheng Hsu of San Jose CA (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Ke Wei Chan of Zhudong Township (TW) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: an apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. the memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.
20240086100.SEQUENCE ALIGNMENT WITH MEMORY ARRAYS_simplified_abstract_(micron technology, inc.)
Inventor(s): Justin Eno of Boise ID (US) for micron technology, inc., Sean S. Eilert of Boise ID (US) for micron technology, inc., Ameen D. Akel of Boise ID (US) for micron technology, inc., Kenneth M. Curewitz of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device may be used to implement a bloom filter. in some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the bloom filter. the memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. the results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
20240086104.DATA SENSING WITH ERROR CORRECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Mauro Castelli of Avezzano (IT) for micron technology, inc., Luigi Pilolli of L’Aquila (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: multiple copies of a stored data are sensed from a subset of memory cells of an array of memory cells into a plurality of latch elements in a page buffer coupled to the array of memory cells. two or more latch elements are selected by enabling a respective select line of each of the two or more latch elements. an output data is determined based on a sensing of the conducting line driven by the two or more latch elements.
Inventor(s): Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Roy Leonard of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0846, G06F12/0882
Abstract: a system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (xlc) storage including a first xlc block and a second xlc storage including a second xlc block, and causing a first portion of the data to be written to a first number of pages of the first xlc block and a second portion of the data to be written to a second number of pages of the second xlc block using page level interleave. the first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first xlc write mode and a second xlc write mode.
Inventor(s): Tony Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/38, G06F9/48, H01L25/065
Abstract: devices and techniques for self-scheduling threads in a programmable atomic unit are described herein. when it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (id) can be passed with the instruction. here, the thread id corresponds to a thread of the instruction. when a response to completion of the instruction is received that includes the thread id, the thread is rescheduled using the thread id in the response.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Mark A. Helm of Santa Cruz CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, H03M13/29
Abstract: systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. in one approach, user data is stored in the first partition of a non-volatile memory. first error correction code data is generated for the user data and stored with the user data in the first partition. second error correction code data is generated for the user data and stored outside the first partition. the second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. a copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. the second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.
20240086315.MEMORY ACCESS STATISTICS MONITORING_simplified_abstract_(micron technology, inc.)
Inventor(s): David A. Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0882, G06F13/16
Abstract: systems, apparatuses, and methods related to memory access statistics monitoring are described. a host is configured to map pages of memory for applications to a number of memory devices coupled thereto. a first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. a second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. the host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
20240086316.MEMORY SUB-SYSTEM WRITE SEQUENCE TRACK_simplified_abstract_(micron technology, inc.)
Inventor(s): Karl D. Schuh of Santa Cruz CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of San Jose CA (US) for micron technology, inc., Jiangang Wu of Fremont CA (US) for micron technology, inc., Kishore K. Muchherla of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06, G06F12/0882
Abstract: a system includes a memory device and a processing device communicatively coupled to the memory device. the processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. the processing device is further to track a sequence in which the number of groups of memory cells were written with the data. in response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.
20240086319.VIRTUAL AND PHYSICAL EXTENDED MEMORY ARRAY_simplified_abstract_(micron technology, inc.)
Inventor(s): Donald M. Morgan of Meridian ID (US) for micron technology, inc., Alan J. Wilson of Boise ID (US) for micron technology, inc., Bryan David Kerstetter of Kuna ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G11C29/10
Abstract: a memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. when extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. the memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. when a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.
20240086324.HIGH BANDWIDTH GATHER CACHE_simplified_abstract_(micron technology, inc.)
Inventor(s): Bryan Hornung of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/0811, G06F12/02, G06F12/06, G06F13/16
Abstract: disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. this increased bandwidth allows for multiple cache operations to be performed in parallel. in some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. in some examples, the hit logic may detect hits for each segment. that is, the hit logic does not correspond to a particular cache segment. each address value may be serviced by any of the plurality of hit logic units.
20240086328.LOADING DATA IN A TIERED MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sudharshan Sankaran Vazhkudai of Austin TX (US) for micron technology, inc., Moiz Arif of Rochester NY (US) for micron technology, inc., Kevin Assogba of Rochester NY (US) for micron technology, inc., Muhammad Mustafa Rafique of Rochester NY (US) for micron technology, inc.
IPC Code(s): G06F12/0862
Abstract: methods, systems, and devices for loading data in a tiered memory system are described. a respective allocation of computing resources may be determined for each node in a cluster, where at least one of the nodes may include multiple memory tiers, and a data set to be processed by the nodes may be analyzed. based on the allocation of computing resources and the analysis of the data set, respective data processing instructions indicating respective portions of the data set to be processed by respective nodes may be generated and sent to the respective nodes. the respective data processing instructions may also indicate a respective distribution of subsets of the respective portions of the data set across the multiple memory tiers at the respective nodes.
20240086330.LATENCY REDUCTION USING STREAM CACHE_simplified_abstract_(micron technology, inc.)
Inventor(s): Muthazhagan BALASUBRAMANI of Singapore (SG) for micron technology, inc., Venkatesh ANANDPADMANABHAN of Singapore (SG) for micron technology, inc.
IPC Code(s): G06F12/0862
Abstract: a system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. an example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
Inventor(s): Lucien J. Bissey of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/14, G06F3/06, G06F21/60, H04L9/06
Abstract: methods, apparatuses, and systems related to data management and security in a memory device are described. data may be stored in a memory system, and as part of an operation to move data from one region to another in the memory system, the data may be validated using one or more hash functions. for example, a memory device may compute a hash value of some stored data, and use the hash value to validate another version of that stored data in the process of writing the other version stored data to a region of the memory system. the memory device may store another hash that is generated from the hash of the stored data and a record of transactions such that transactions are identifiable; the sequence of transactions within the memory system may also be identifiable. hashes of transactions may be stored throughout the memory system or among memory systems.
Inventor(s): Kinyue Szeto of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F13/16
Abstract: a processing device in a memory sub-system retrieves an input/output (io) instruction of a plurality of io instructions from an io instruction memory in the memory sub-system, the io instruction comprising a first number of bits. the processing device further generates an io vector based on the io instruction, the io vector comprising a second number of bits, wherein the second number of bits is greater than the first number of bits. in addition, the processing device causes a plurality of io signals, based on the io vector, to be driven on a signal communication bus to a memory device in the memory sub-system, wherein the plurality of io signals comprises a number of signals equal to the second number of bits of the io vector.
Inventor(s): Bryan Hornung of Plano TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F15/78, G06F7/498, G06F13/16, G06F13/40, G06F15/173
Abstract: a reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. the tiles can be arranged in an array or grid and can be communicatively coupled. in an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. the passthrough bus can extend through intervening tiles.
20240086689.STEP-AHEAD SPIKING NEURAL NETWORK_simplified_abstract_(micron technology, inc.)
Inventor(s): Dmitri Yudanov of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06N3/04, G06N3/063, G06N3/08
Abstract: the disclosed embodiments include a memory array configured to store a membrane potential and a synaptic connection identifier of each of a plurality of neurons, a plurality of processors coupled to the memory array, the plurality of processors configured to: immediately perform a search and match operation in the memory array upon receiving a spike message identifying relevant synaptic connections in the memory array, generate a bitmask signifying a first source neuron identifier having a match to a second source neuron identifier in the memory array, perform a synaptic integration and a long-time depression computation on a subset of spike messages including the first spike message, update membrane potentials of the plurality of neurons upon receiving an indication that all the spike messages identified in a barrier message have been received in the memory array, generate a new spike message, and transmit the new spike message to a network.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/3745, G06N3/063, H04N5/369, H04N5/378
Abstract: a method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/063
Abstract: a device configured with redundant computations to improve reliability of using memory cells to perform operations of multiplication and accumulation. the device can have a memory cell array and a logic circuit. each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation and programmable in a second mode, different from the first mode, to store data. the memory cell array has a plurality of regions operable in parallel to perform redundant operations of multiplication and accumulation. the logic circuit is configured to compare a plurality of results, generated from the redundant operations of multiplication and accumulation performed using the plurality of regions respectively, to select an output result from the plurality of results.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V10/94, G06F7/544, G06N3/04, G06N3/063, G06V10/774, G06V10/776, G06V10/778, G06V10/82, H04N5/374
Abstract: a method to balance computation accuracy and energy consumption, including: programming thresholds voltages of first memory cells to store first weight matrices representative of a first artificial neural network; programming thresholds voltages of second memory cells to store second weight matrices representative of a second artificial neural network smaller than the first artificial neural network, where both the first artificial neural network and the second artificial neural network are operable to provide at least one common functionality in processing each of the inputs; selecting configurations of using the first memory cells, or the second memory cells, or both in processing a sequence of inputs; and performing, according to the configurations, operations of multiplication and accumulation using the first memory cells, and the second memory cells in computations of the first artificial neural network and the second artificial neural network in processing the sequence of the inputs.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V20/52, G06N5/04
Abstract: a surveillance camera having: an image sensing pixel array operable to generate first data representative of an input image; a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image; voltage drivers; current digitizers; an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells programmed in the first mode to store the weight matrices used in generation of the output image; a transceiver; and a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array.
Inventor(s): Junichi Sato of Yokohama (JP) for micron technology, inc.
IPC Code(s): G07C5/08, B60W50/02, G05D1/00, G06F3/06, G07C5/00
Abstract: a method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; automatically collecting, by a memory device, data generated by the at least one system, where the data is collected by the memory device independently of control by the host system; and storing the data in the memory device.
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Maurizio Rizzi of Cologno Monzese (IT) for micron technology, inc.
IPC Code(s): G11C7/10, G06F17/16
Abstract: apparatuses, methods, and systems for matrix formation for performing computational operations in memory are included. an embodiment includes a memory having a plurality of levels, wherein each of the plurality of levels includes a plurality of memory cells, voltage circuitry configured to apply sub-threshold voltages to the memory cells of each respective level, a plurality of sense lines, sense circuitry coupled to the plurality of sense lines, wherein the sense circuitry coupled to each respective sense line is configured to sense a state for each of the number of memory cells coupled to that respective sense line responsive to the voltage circuitry applying the sub-threshold voltages to the memory cells of each respective level, and processing circuitry configured to utilize the states for each of the memory cells to form a matrix and perform computational operations on data stored in the memory using the matrix.
Inventor(s): Brian W. Huber of Allen TX (US) for micron technology, inc., Scott E. Smith of Plano TX (US) for micron technology, inc., Gary L. Howe of Allen TX (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: a memory device includes a command interface configured to receive write commands from a host device. additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. furthermore, the memory device includes a first ripple counter and a second ripple counter. the memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. the command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C7/10, G06F7/544, G11C7/12
Abstract: a device having a memory cell array configured with inverted weight data for operations of multiplication and accumulation. each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation. the memory cell array has a plurality of regions operable in parallel to perform operations of multiplication and accumulation. the plurality of regions include a first region and a second region. at least a second portion of weight bits stored in the second region is an inverted version of a first portion of weight bits stored in the first region. the device includes a logic circuit configured to adjust a computation result of multiplication and accumulation generated using the second region to account for weight inversion and generate an output result based on a plurality of results generated using the plurality of regions respectively.
20240087625.TEST MODE SECURITY CIRCUIT_simplified_abstract_(micron technology, inc.)
Inventor(s): Kari Crane of Meridian ID (US) for micron technology, inc., Kevin G. Werhane of Kuna ID (US) for micron technology, inc., Yoshinori Fujiwara of Boise ID (US) for micron technology, inc., Jason M. Johnson of Nampa ID (US) for micron technology, inc., Takuya Tamano of Boise ID (US) for micron technology, inc., Daniel S. Miller of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/24, G11C7/10, G11C17/16
Abstract: an apparatus includes a tm control circuit that is configured to receive address information corresponding to a tm function and compare the address information with an authorized tm list stored in a memory of the apparatus to determine if there is a match. if there is a match, a latch load signal pulse is output. a tm latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. the tm latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the tm function. the apparatus includes a plurality of tm functions for testing various features of the apparatus and the authorized tm list identifies which of the plurality of tm functions has been authorized for customer use.
20240087643.SEQUENCE ALIGNMENT WITH MEMORY ARRAYS_simplified_abstract_(micron technology, inc.)
Inventor(s): Justin Eno of Boise ID (US) for micron technology, inc., Sean S. Eilert of Boise ID (US) for micron technology, inc., Ameen D. Akel of Boise ID (US) for micron technology, inc., Kenneth M. Curewitz of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C13/00, C12Q1/6869, G11C7/16, G16B30/10
Abstract: a memory device may be used to implement a bloom filter. in some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the bloom filter. the memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. the results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Dung V. Nguyen of San Jose CA (US) for micron technology, inc., Giovanni Maria Paolucci of Milano (IT) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Tomoharu Tanaka of Kanagawa (JP) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/32
Abstract: exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. the adaptive pre-read manager receives a first set of data bits for programming to memory. the adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. the adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. the adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. the adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C16/12, G06F7/544, G11C16/24, G11C16/26
Abstract: an integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. the integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. during a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.
Inventor(s): Nagendra Prasad Ganesh Rao of Folsom CA (US) for micron technology, inc., Paing Z. Htet of Union City CA (US) for micron technology, inc., Sead Zildzic, JR. of Folsom CA (US) for micron technology, inc., Thomas Fiala of Folsom CA (US) for micron technology, inc., Jian Huang of Union City CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/08, G11C16/16
Abstract: a system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. the operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
20240087663.BUILT-IN SELF-TEST CIRCUITRY_simplified_abstract_(micron technology, inc.)
Inventor(s): William Yu of Boise ID (US) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Thomas T. Tangelder of Boise ID (US) for micron technology, inc., Jacob S. Robertson of Caldwell ID (US) for micron technology, inc., James G. Steele of Boise ID (US) for micron technology, inc., Joemar Sinipete of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/36, G11C29/02, G11C29/42
Abstract: methods, systems, and devices related to built-in self-test (bist) circuitry of a controller. the controller can be coupled to multiple memory devices. the bist circuitry can include registers configured to store burst patterns. the bist circuitry can perform a bist operation on the memory devices contemporaneously and using the number of burst patterns.
Inventor(s): William Yu of Boise ID (US) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc., Chad B. Erickson of Boise ID (US) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc.
IPC Code(s): G11C29/38, G11C29/10, G11C29/12
Abstract: methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. a controller can be coupled to a memory device. the controller can include built-in self-test (bist) circuitry. the bist circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.
[[20240087948.Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry_simplified_abstract_(micron technology, inc.)]]
Inventor(s): David H. Wells of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/764, H01L21/02, H01L21/20
Abstract: some embodiments include methods of forming voids within semiconductor constructions. in some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00
Abstract: systems and methods for a semiconductor device having a front-end-of-line structure are provided. the semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. the interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. the semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.
Inventor(s): Lifang Xu of Boise ID (US) for micron technology, inc., Bo Zhao of Boise ID (US) for micron technology, inc., Jeffrey D. Runia of Boise ID (US) for micron technology, inc., Nancy M. Lomeli of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/535
Abstract: a microelectronic device includes a stack structure including a block region and a non-block region. the block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. at least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. the non-block region neighbors the block region in the first horizontal direction. the non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. related memory devices, electronic systems, and methods are also described.
Inventor(s): Collin Howder of Boise ID (US) for micron technology, inc., Taehyun Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01L23/528, H01L27/11556, H01L27/11582
Abstract: methods, systems, and devices for access circuitry structures for three-dimensional (3d) memory arrays are described. a memory device may include levels of memory cells over a substrate. to support accessing memory cells at respective levels, the memory device may include a conductive pillar extending through the levels of memory cells and coupled with one or more memory cells at respective levels of memory cells. the memory device may include a bit line and a contact that is configured to couple the bit line with the conductive pillar. the conductive pillar may be formed such that it extends into a portion of the contact, and a contact resistance between the conductive pillar and the bit line may be based on the conductive pillar extending into the portion of the contact.
20240088072.EMBEDDED METAL PADS_simplified_abstract_(micron technology, inc.)
Inventor(s): Tsung Han Chiang of Taichung City (TW) for micron technology, inc., Shin Yueh Yang of Taichung City (TW) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: methods, apparatuses, and systems related to embedded metal pads are described. an example semiconductor device includes a dielectric material, a metal pad having side surface, where a lower portion of the side surface is embedded in the dielectric material, a mask material on a portion of a surface of the dielectric material, an upper portion of the side surface of the metal pad, and a portion of a top surface of the metal pad and a contact pillar on a second portion of the top surface of metal pad, the contact pillar comprising a metal pillar and a pillar bump.
Inventor(s): Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/48, H01L25/00, H01L25/065
Abstract: an interface shim layer for a tightly-coupled random access memory device is disclosed. the interface shim layer redirects and coalesces integrated channels and connections between a stacked plurality of memory die and an application specific integrated circuit and directly connects to the memory die and to the application specific integrated circuit. a passive version of the interface shim layer incorporates a plurality of routing layers to facilitate routing of signals to and from the stacked plurality of memory die and the application specific integrated circuit. an active version of the interface shim layer incorporates separate physical interfaces for both the stacked plurality of memory die and the application specific integrated circuit to facilitate routing. the active version of the interface shim layer may further incorporate memory controller functions, built-in self-test circuits, among other capabilities that are migratable into the active interface shim layer.
20240088211.OVER-SCULPTED STORAGE NODE_simplified_abstract_(micron technology, inc.)
Inventor(s): Devesh Dadhich Shreeram of Meridian ID (US) for micron technology, inc., Sanjeev Sapra of Boise ID (US) for micron technology, inc., Kangle Li of Boise ID (US) for micron technology, inc., Sevim Korkmaz of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L49/02
Abstract: methods, apparatuses, and systems related to an over-sculpted storage node are described. an example method includes forming an opening in a pattern of materials. the method further includes performing an etch to over-sculpt the opening. the method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. the method further includes performing an etch to remove portions of the pattern of materials. the method further includes performing an etch on the storage node material to trim the over-sculpted storage node.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/3745, H04N5/357, H04N5/369
Abstract: a method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/378, G06T9/00, H04N5/341
Abstract: a method in an integrated circuit device to compress images, including: generating, by an image processing logic circuit and based on first data representative of an input image, input data; generating, by an inference logic circuit and based on the input data, a column of inputs; converting, by the inference logic circuit using voltage drivers connected to wordlines and memory cells storing a weight matrix, and into output currents of the memory cells summed in bitlines, results of bitwise multiplications of bits in the column of inputs and bits stored in the memory cells in a form of threshold voltages of the memory cells; digitizing currents summed in the bitlines to obtain column outputs; generating, by the inference logic circuit, output data based on the column outputs; and generating, using the output data, second data representative of an output image compressed from the input image.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/3745, H01L23/00, H01L27/146
Abstract: an integrated circuit device including: a first integrated circuit die having an image sensing pixel array; a second integrated circuit die having an image processing logic circuit and an inference logic circuit; and a third integrated circuit die having a memory cell array. the second integrated circuit die and the third integrated circuit die are connected via a direct bond interconnect. the inference logic circuit is configured to process an image from the image sensing pixel array via multiplication and accumulation operations based on memory cells in the memory cell array having threshold voltages programmed to store data in multiplications and output currents from the memory cells connected to lines in summations.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/3745, G06F3/06, H04N5/369, H04N5/376
Abstract: an integrated circuit device having a memory cell array with first layers of memory cells configured for operations of multiplication and accumulation. each pair of closest layers among the first layers are configured to be separate by at least one layer in second layers of memory cells, where access to, or usages of, the second layers can be restricted or limited to prevent activities in the second layers from corrupting the weight programming in the first layers.
20240089634.Monitoring of User-Selected Conditions_simplified_abstract_(micron technology, inc.)
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N5/3745, G06N3/08, G06V10/764, G06V10/82, G06V10/94, G11C7/10, G11C11/54
Abstract: a method for a digital camera adaptable to monitor a scene to detect a condition of interest to a user. the digital camera can program, in a first mode, first memory cells according to first weight matrices to classify images captured by the digital camera. second memory cells are programmed in a second mode to store data representative of the images. the digital camera can perform operations of multiplication and accumulation using the first memory cells to compute first classifications of the images. in response to mismatches between the first classifications and second classifications identified by the user for the images, the digital camera can execute instructions to determine second weight matrices and program, in the first mode, third memory cells, according to the second weight matrices for improved capability in detecting the condition represented by image classifications in a predetermined category.
Inventor(s): Harutaka Honda of Hiroshima (JP) for micron technology, inc., SHOGO OMIYA of Hiroshima (JP) for micron technology, inc., SHOKO NORIFUSA of Hiroshima (JP) for micron technology, inc., HIDEKAZU NOBUTO of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L27/108
Abstract: an apparatus includes: a plurality of capacitors each including first and second conductive portions and a dielectric portion therebetween; a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors; a second conductive structure on a top surface of the first conductive structure; and a third conductive structure on a top surface of the second conductive structure.
Inventor(s): Yoshikazu Moriwaki of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L27/108
Abstract: a microelectronic device is disclosed, comprising a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; a transistor structure comprising: a channel within one of the active regions of the base structure and horizontally interposed between two of the isolation regions; a gate dielectric structure including a high-k material above the channel; a gate electrode stack on the gate dielectric structure and comprising: diffusion prevention material on the gate dielectric structure and partially horizontally overlapping the channel, an opening in the diffusion prevention material horizontally centered about a horizontal centerline of the channel and having a smaller horizontal dimension than the channel; a conductive material comprising lanthanum on the diffusion prevention material and substantially filling the opening.
Micron Technology, Inc. patent applications on March 14th, 2024
- Micron Technology, Inc.
- G06F3/06
- Micron technology, inc.
- G06F12/0846
- G06F12/0882
- G06F9/38
- G06F9/48
- H01L25/065
- G06F11/10
- H03M13/29
- G06F12/02
- G06F13/16
- G11C29/10
- G06F12/0811
- G06F12/06
- G06F12/0862
- G06F12/14
- G06F21/60
- H04L9/06
- G06F15/78
- G06F7/498
- G06F13/40
- G06F15/173
- G06N3/04
- G06N3/063
- G06N3/08
- H04N5/3745
- H04N5/369
- H04N5/378
- G06V10/94
- G06F7/544
- G06V10/774
- G06V10/776
- G06V10/778
- G06V10/82
- H04N5/374
- G06V20/52
- G06N5/04
- G07C5/08
- B60W50/02
- G05D1/00
- G07C5/00
- G11C7/10
- G06F17/16
- G11C7/12
- G11C7/24
- G11C17/16
- G11C13/00
- C12Q1/6869
- G11C7/16
- G16B30/10
- G11C16/10
- G11C16/26
- G11C16/32
- G11C16/12
- G11C16/24
- G11C16/08
- G11C16/16
- G11C29/36
- G11C29/02
- G11C29/42
- G11C29/38
- G11C29/12
- H01L21/764
- H01L21/02
- H01L21/20
- H01L23/48
- H01L21/768
- H01L23/00
- H01L23/528
- H01L23/535
- H01L27/11556
- H01L27/11582
- H01L25/00
- H01L49/02
- H04N5/357
- G06T9/00
- H04N5/341
- H01L27/146
- H04N5/376
- G06V10/764
- G11C11/54
- H01L27/108
- G06F3/0679
