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Category:G01R31/3177
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Pages in category "G01R31/3177"
The following 15 pages are in this category, out of 15 total.
1
- 17851860. TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
- 18152017. BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
- 18244994. DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME simplified abstract (MEDIATEK INC.)
- 18368195. 3D TAP & SCAN PORT ARCHITECTURES simplified abstract (Texas Instruments Incorporated)
- 18403623. SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
- 18447955. FLIP FLOP STANDARD CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
- 18524900. INTERPOSER CIRCUIT simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
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- Taiwan semiconductor manufacturing co., ltd. (20240097661). BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD simplified abstract
- Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 21st, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on April 25th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 29th, 2024