18244994. DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME simplified abstract (MEDIATEK INC.)
Contents
- 1 DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME
Organization Name
Inventor(s)
Anshul Varma of San Jose CA (US)
Hsin Chen Chen of San Jose CA (US)
DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18244994 titled 'DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME
Simplified Explanation
The patent application describes a method, computer-readable medium, and apparatus for performing a scan test on a chip, where the apparatus includes an internal voltage source that generates an internal voltage based on a constant voltage. The internal voltage is maintained at a lower level during the capture phase of the scan test, increased to a high voltage level at the start of the shift phase, and then reduced back to the lower level at the end of the shift phase.
- Internal voltage source on the same die of the chip
- Constant voltage input to the internal voltage source
- Internal voltage maintained at a lower level during the capture phase
- Internal voltage increased to a high level at the start of the shift phase
- Internal voltage reduced back to the lower level at the end of the shift phase
Potential Applications
This technology could be applied in the semiconductor industry for testing and quality control of chips.
Problems Solved
This technology helps in accurately testing chips by controlling the internal voltage levels during different phases of the scan test.
Benefits
- Improved accuracy in chip testing - Efficient control of internal voltage levels - Enhanced quality control in chip manufacturing
Potential Commercial Applications
"Enhancing Chip Testing Through Internal Voltage Control"
Possible Prior Art
There may be prior art related to internal voltage control in chip testing, but specific examples are not provided in the abstract.
Unanswered Questions
How does the internal voltage source impact the overall performance of the chip during the scan test?
The article does not delve into the potential effects of the internal voltage source on the chip's performance beyond the scan test.
Are there any limitations to using this internal voltage source in chip testing?
The article does not address any potential drawbacks or limitations of implementing this internal voltage source in chip testing processes.
Original Abstract Submitted
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus is used for performing a scan test on a chip. In certain configurations, the apparatus includes an internal voltage source on a same die of the chip. The internal voltage source receives a constant voltage. The internal voltage source generates an internal voltage based on the constant voltage. The internal voltage is maintained at a lower voltage level in a capture phase of the scan test, and is increased from the lower voltage level to a high voltage level at a start of a shift phase of the scan test and reduced from the high voltage level to the lower voltage level at an end of the shift phase.
