Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 21st, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on March 21st, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 120 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (39), H01L29/78 (27), H01L27/092 (23), H01L29/06 (19), H01L23/00 (19)
With keywords such as: layer, structure, semiconductor, gate, dielectric, substrate, region, conductive, device, and metal in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Jen-Chun Wang of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Lien Lee of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chien Chi of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Wen Su of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): C23C14/35, C23C14/00, C23C14/04, C23C14/06, C23C14/22, C23C14/34, C23C16/04, C23C16/34, C23C16/455, H01J37/34, H01L21/02, H01L21/285, H01L21/67, H01L21/768
Abstract: a semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. in embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. in other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.
Inventor(s): Ankita PATIDAR of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sandeep Kumar GOEL of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/28, G01R31/317, G06F30/398
Abstract: a method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. the burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. the integrated circuit design corresponding to the integrated circuit. the performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. the heat signature includes heat values distributed throughout the integrated circuit design.
Inventor(s): Ching-Fang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Tai LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/28, H01L21/66, H01L23/00, H01L23/12, H01L23/498
Abstract: a circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. the circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. the circuit test structure further includes a test structure connected to the conductive line. the circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.
Inventor(s): Eugene I-Chun Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Liang Liu of Pingtung City (TW) for taiwan semiconductor manufacturing co., ltd., De-Yang Chiou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Lung Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Shiung Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/122, G02B6/13, G02B6/136
Abstract: a semiconductor-on-insulator (soi) structure and a method for forming the soi structure. the method includes forming a first dielectric layer on a first semiconductor layer. a second semiconductor layer is formed over an etch stop layer. a cleaning solution is provided to a first surface of the first dielectric layer. the first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. an index guiding layer may be formed over the second semiconductor layer. a third semiconductor layer is formed over the second semiconductor layer. a distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. a planarization process is performed on the third semiconductor layer to reduce the maximum distance.
Inventor(s): Hsing-Kuo Hsia of Jhubei CIty (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jui Lin Chao of NewTaipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/132, G02B6/12, G02B6/136, H01L21/768, H01L23/48, H01L25/16
Abstract: a method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. the substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. the method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. the openings are filled with a dielectric material to form dielectric regions. through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.
Inventor(s): Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ping-Hsun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/44, G03F1/42, G03F1/84
Abstract: a method of making a semiconductor device includes forming at least one fiducial mark on a photomask. the method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. the defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.
Inventor(s): Pei-Cheng HSU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hao LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Ling LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/62, B82Y30/00, H01L21/027
Abstract: a pellicle for an extreme ultraviolet (euv) photomask includes a pellicle frame and a main membrane attached to the pellicle frame. the main membrane includes a plurality of nanotubes, and each of the plurality of nanotubes is covered by a coating layer containing si and one or more metal elements.
Inventor(s): Tzu-Ang CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Ching CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/64, G03F1/62
Abstract: a pellicle for an euv photo mask includes a first layer; a second layer; and a main layer disposed between the first layer and second layer and including a plurality of nanotubes. at least one of the first layer or the second layer includes a two-dimensional material in which one or more two-dimensional layers are stacked. in one or more of the foregoing and following embodiments, the first layer includes a first two-dimensional material and the second layer includes a second two-dimensional material.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Haruki MORI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Chang ZHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F3/06
Abstract: a circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits n. a signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to n−1, and values of the second sequence decrement from n−1 to zero. a selection circuit coupled to the data register is configured to output the n bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.
Inventor(s): Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/3308
Abstract: a method of using a semiconductor device characterization description is disclosed. the method includes accessing the semiconductor device characterization description, accessing a first starter code, generating a first model authentication code (mac) based on the semiconductor device characterization description and the first starter code, and transmitting the first starter code, the first mac, and the semiconductor device characterization description to a model interface (mi).
Inventor(s): Chih-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Hsuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/39, G06F30/392, G06F30/394, G06F30/398, H01L29/40
Abstract: an integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. the first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. a distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.
Inventor(s): Yu-Tao YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Shen CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G03F1/36, G06F30/39, G06F30/392
Abstract: a device includes a first cell active area asymmetrically positioned in a first device column between a first barrier line and a second barrier line, a second cell active area asymmetrically positioned in a second device column between the first barrier line and a third barrier line, where the first cell has a first cell length in a first direction perpendicular to the first barrier line which is three times a second cell length in the first direction. the first cell active area and the second cell active area are a first distance from the first barrier line, and the first cell active area is a second distance from the second barrier line, and the second cell active area is the second distance away from the third barrier line.
Inventor(s): Wei-Yi HU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ming CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chou TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G03F1/36, G06F30/392
Abstract: disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance lin which the first dummy pattern includes n dummy conductors having a first dummy conductor length lwith the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing ee.
20240096383.MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/10, G11C5/06
Abstract: a memory device includes a first static random access memory (sram) cell, a second sram cell, and a first metal layer. the first sram cell includes a first write-port pull-up (pu) transistor and a second write-port pu transistor arranged in a y-direction, and a first read-port pd transistor and a first read-port pg transistor. the second sram cell includes a third write-port pu transistor and a fourth write-port pu transistor arranged in the y-direction, and a second read-port pd transistor and a second read-port pg transistor. the first and second read-port pd transistors and the first and second read-port pg transistors are arranged in the y-direction. the first metal layer is over the first sram cell and the second sram cell. the first metal layer includes a read bit-line conductor extending in the y-direction and shared by the first sram cell and the second sram cell.
Inventor(s): Yi-Ching LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C8/08, G11C8/10
Abstract: a memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. the memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.
Inventor(s): Bo-Feng YOUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-I WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/22, H10B51/30
Abstract: a memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. the read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. the write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
Inventor(s): Chien-Yuan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hau-Tai SHIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng Hung LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/4091, G11C11/4093, G11C11/4094
Abstract: a memory device includes a memory bank with a memory cell connected to a local bit line and a word line. a first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. a word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. a first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. a global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. a bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.
Inventor(s): Chun-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Gu-Huan LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Yu CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/18, G11C17/16
Abstract: a memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. the comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. the comparator including a first input terminal and a first output terminal. the first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. the first output terminal is configured to output the first output signal. the detection circuit is coupled to the comparator and the non-volatile memory cell. the detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. the detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.
Inventor(s): Yen-Liang LIN of Yilan County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Kang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chuan TAI of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/34, C23C14/18, C23C14/35, C23C14/54, H01J37/32
Abstract: the physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. during a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. the physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.
Inventor(s): Chieh-Hsin HSIEH of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/075, G03F7/16, H01L21/308, H01L21/311, H01L21/3213
Abstract: a method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. a second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. a photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.
Inventor(s): Bao-Chin LI of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Kai HUANG of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Ko-Pin KAO of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yen HSAIO of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/033, H01L21/027, H01L21/28, H10B41/35, H10B41/43
Abstract: a photo mask includes a plurality of device features, a first assist feature, and a second assist feature. the device features are in a patterning region of a device region. the first assist feature are in the patterning region and adjacent to the device features. the first assist feature is for correcting an optical proximity effect in a photolithography process. the second assist feature is in a non-patterning region of the device region. the second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features.
Inventor(s): Li-Wei Yin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Wen Pan of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsien Lin of Kaohusiung (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Shih Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Jih-Sheng Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Chieh Chao of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Yih-Ann Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/28, H01L21/285, H01L29/49, H01L29/66, H01L29/78
Abstract: disclosed is a semiconductor fabrication method. the method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.
Inventor(s): Jing-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Lin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/321, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L25/00, H01L25/10
Abstract: some embodiment structures and methods are described. a structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. the redistribution structure is electrically coupled to the integrated circuit die. the redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. the metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. the second dielectric layer is a photo-sensitive material. the metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.
Inventor(s): Alexander KALNITSKY of San Francisco CA (US) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng WU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Harry-Hak-Lay CHUANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/321, H01L21/8234, H01L27/088, H01L29/49, H01L29/66, H01L29/78
Abstract: a semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. the first well and the second well are within the substrate. the metal gate is partially over the first well. the poly gate is over the second well. the poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. the source region and the drain region are respectively within the first well and the second well.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/48, H01L21/02, H01L21/8249
Abstract: the present disclosure describes a method of forming an epitaxial layer on a substrate in a chamber. the method includes cleaning the chamber with a first etching gas and depositing the epitaxial layer on the substrate. deposition of the epitaxial layer includes epitaxially growing a first portion of the epitaxial layer with a precursor, cleaning the substrate and the chamber with a flush of a second etching gas different from the first etching gas, and epitaxially growing a second portion of the epitaxial layer with the precursor. the first portion and the second portion have the same composition. the method furthers includes etching a portion of the epitaxial layer with a third etching gas having a flow rate higher than that of the second etching gas.
Inventor(s): Mirng-Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Lung-Kai Mao of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/48, H01L23/00, H01L23/498, H01L23/522, H01L23/538
Abstract: a method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. the first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. the first package component is bonded to a second package component.
Inventor(s): Chia-Cheng Chen of Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kai Yang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Yin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/68, G06T1/00, G06T7/00, G06T7/73, H01L23/544
Abstract: a method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. in an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
Inventor(s): Yu-Lien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei Hsiang Chan of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522
Abstract: provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. an exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.
Inventor(s): Joanna Chaw Yane YIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hua Feng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/8238, H01L23/485, H01L23/532, H01L23/535, H01L27/092, H01L29/66, H01L29/78
Abstract: devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. the liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. in an embodiment, the filled opening provides a contact structure.
Inventor(s): Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Wen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/48, H01L29/40, H01L29/417, H01L29/66
Abstract: a device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
Inventor(s): Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Yui Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Chung Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Cheng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chung Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ping Chen of Toucheng Township (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Chia Tseng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ching Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L29/423, H01L29/66, H01L29/786
Abstract: a semiconductor device includes a plurality of channel layers vertically separated from one another. the semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. the lower portion wraps around each of the plurality of channel layers. the semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. the gate spacer has a bottom surface. moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. the dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
Inventor(s): Ming-Chi Huang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Bin Huang of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Liang Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/3213, H01L21/8238, H01L29/66, H01L29/78
Abstract: a method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. an anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. a footing portion of the third portion remains after the anisotropic etching. the method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.
Inventor(s): Wen-Hsien TU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Dong-Jie KE of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/08
Abstract: an integrated circuit device is provided. the integrated circuit device includes a semiconductor substrate, first and second semiconductor fins over the semiconductor substrate, and first and second epitaxy structures respectively on the first and second semiconductor fins. the first epitaxy structure is merged with the second epitaxy structure, and a bottom surface of the second epitaxy structure is lower than a bottom surface of the first epitaxy structure.
Inventor(s): Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chieh-Fang Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Chung Ho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pin-Cheng Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/84, H01L23/522, H01L27/12
Abstract: provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. the gate electrode is located within a first dielectric layer that overlies a substrate. the gate dielectric layer is located over the gate electrode. the channel layer is located on the gate dielectric layer. the insulating layer is located over the channel layer. the first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. the second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. the stop segment is embedded in the second dielectric layer.
Inventor(s): Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Hui Huang of Yilan County (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Yun Hou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Yuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/04, H01L21/52, H01L23/31, H01L23/538, H01L25/065
Abstract: a semiconductor device includes a first substrate, an electronic component, and a lid. the first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. the electronic component is coupled to the first substrate top side and coupled to the connector structure. the lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.
Inventor(s): Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hui Lin of Shengang Township (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Peng Tai of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L21/321, H01L23/00, H01L23/498, H01L23/538, H01L25/065
Abstract: in an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. the package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.
20240096731.SEMICONDUCTOR PACKAGE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng HSU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu JENG of Po-Shan Village, Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Yi LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/31, H01L23/373, H01L23/433, H01L25/065, H01L25/10
Abstract: a semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. the first thermal interface material and the second thermal interface material have an identical width.
Inventor(s): Chih-Hao CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Hui CHENG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Ching SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/498, H01L25/10, H10B80/00
Abstract: some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. the semiconductor die package is mounted to an interposer. in addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. the fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. the footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.
Inventor(s): Chao-Wei Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Wei Li of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/38, H01L23/48, H01L23/498, H10N10/82
Abstract: provided is a package structure including a first redistribution layer (rdl) structure, a die, a circuit substrate, and a first thermoelectric cooler. the rdl) structure has a first side and a second side opposite to each other. the die is disposed on the first side of the first rdl structure. the circuit substrate is bonded to the second side of the first rdl structure through a plurality of first conductive connectors. the first thermoelectric cooler is between the first rdl structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a n-type doped region and at least a p-type doped region.
Inventor(s): Harry-Haklay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Shiang-Hung Huang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin Fu Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/762, H01L21/768, H01L23/522
Abstract: the present disclosure provides a semiconductor device. the semiconductor device includes: a substrate having a device area and a peripheral area surrounding the device area; a via, disposed at the peripheral area and extending at least partially through the substrate; an insulating structure, disposed at the peripheral area, extending at least partially through the substrate and surrounding the via; and a doped region, disposed at the peripheral area, over or in the substrate and adjacent to the via.
Inventor(s): Chih-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Syuan CIOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Wen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768
Abstract: a method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. the method further includes depositing a spacer material against a sidewall of the first transistor. the method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. the method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. the method further includes manufacturing a self-aligned interconnect structure (sis) extending along the spacer material, wherein the spacer material separates a portion of the sis from the first transistor, and the first electrical connection directly contacts the sis.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Chiang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hong-Chen CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jonathan Tsung-Yung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lee-Chung LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, G11C11/418, H01L21/768, H10B10/00
Abstract: an integrated circuit (ic) die includes first through third adjacent rows of through-silicon vias (tsvs), and first and second adjacent rows of memory macros. tsvs of the first row of tsvs extend through and are electrically isolated from memory macros of the first row of memory macros. tsvs of the third row of tsvs extend through and are electrically isolated from memory macros of the second row of memory macros.
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hui Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/495, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/538
Abstract: a semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. the chip includes conductive posts exposed at an active surface. the redistribution structure is disposed on the active surface. the redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. the first dielectric layer includes first openings exposing the conductive posts of the chip. the topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. the topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. the second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. the first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.
Inventor(s): Ya-Huei LEE of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Ching HSU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Shyue-Ter LEU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498
Abstract: a semiconductor die package is provided. the semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. the semiconductor die has a corner. the package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. the first line segment is linear and extends in a first direction. the second line segment is non-linear and has a varying extension direction.
20240096781.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chun-Ti Lu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Jiun Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Wei Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Chun Cho of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Rong Ni of Chiayi County (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Wei Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Zheng-Gang Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tai-You Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chang Shih of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H10B80/00
Abstract: a package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. the semiconductor die is laterally encapsulated by an insulating encapsulation. the redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. the redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. the electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
Inventor(s): Meng-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Tsong Wang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Hua Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ko Chun Liu of Toufen Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L27/146
Abstract: some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. the extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. the extended via finds application for capacitor arrays used for pixel circuits.
Inventor(s): Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hung LIN of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Min HUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Jung HSUEH of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao TSAI of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Sheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/48, H01L23/00
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. the conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. the semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. the lower conductive via is electrically connected to the conductive pillar through the upper conductive via. the conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. a top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
Inventor(s): Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Ying CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/525, H01L21/768
Abstract: an antifuse structure and ic devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.
Inventor(s): Fei Fan DUAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fong-yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hsiang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, G06F30/398, H01L23/522
Abstract: a semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.
Inventor(s): Sheng-Hsiung Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui Kao of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Nan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jack Liu of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, G06F30/392, G06F30/394, H01L21/768, H01L23/522
Abstract: an integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. the first interconnect structure includes multiple frontside metal layers. the second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. in some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-manhattan-diagonal routing. a variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
Inventor(s): Chung-Hui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, G06F30/392, H01L27/092, H01L29/06, H01L29/423, H01L29/786
Abstract: a semiconductor device includes a first conductive line extending in a first direction on a front side of a semiconductor wafer, a first power rail extending in the first direction on a back side of the semiconductor wafer, and a first transistor including a first gate structure extending in a second direction perpendicular to the first direction, first and second active regions adjacent to the first gate structure, and a first channel region extending between the first and second active regions through the first gate structure. a first via is positioned between and electrically connects the first active region and the first conductive line, and a second via is positioned between and electrically connects the second active region and the first power rail.
Inventor(s): Shang-Wen Chang of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun Chiu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Wei Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/02, H01L21/8238, H01L23/00, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: in an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
Inventor(s): Kuan-Chung Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Tao Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Shih Yeh of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/31, H01L25/065
Abstract: the present disclosure provides a package structure and a method of manufacturing a package. the package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. the redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. the bumps are disposed on the redistribution structure. the redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. the redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.
Inventor(s): Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L23/00, H01L23/31, H01L25/18
Abstract: a method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
Inventor(s): Jing-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/544, H01L23/00, H01L23/31
Abstract: a semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. the mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. in another embodiment the mark is formed using a wobble scan methodology. by forming marks as described, defects from the marking process may be reduced or eliminated.
20240096822.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chia-Kuei HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Che-Chia YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao LIN of Zhudong Township Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/065
Abstract: a package structure is provided. the package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. in a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
Inventor(s): Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hang TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung YEE of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yian-Liang KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Yi WU of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L25/04
Abstract: a bond head is provided. the bond head includes a bond base, a chuck member, and an elastic material. the chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. in the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. the elastic material is disposed over the chuck surface. the elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.
Inventor(s): Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Li Yang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chen Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/31
Abstract: in an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.
Inventor(s): Yu-Yi Huang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hung Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ming Wang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chen Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Peng Tai of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/304, H01L25/065
Abstract: a method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. at a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. an edge trimming process is then performed on the wafer stack. after the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. an interconnect structure is formed as a part of the second wafer. the interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
Inventor(s): Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan-Ning Shih of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/498, H01L23/538
Abstract: a package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. the redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. the conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. the first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
Inventor(s): Chih-Wei Wu of Zhuangwei Township (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Feng Yang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/065
Abstract: a method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.
Inventor(s): Wei-Chung Chang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/768, H01L23/00, H01L23/498, H01L23/538
Abstract: a semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. the redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. the terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (ubm) and a capping layer. the ubm is disposed on and electrically coupled to the redistribution circuit structure, where the ubm includes a recess. the capping layer is disposed on and electrically coupled to the ubm, where the ubm is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the ubm.
Inventor(s): Wei-Hsin TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L21/8238, H01L23/522, H01L27/092
Abstract: a semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. the first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. the second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. the drain/source contact extends in the second direction and is connected to the second conductor. the at least one conductive via connects the first conductor and the second conductor through the third conductor.
Inventor(s): Guo-Huei WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, G06F30/392, G06F30/394, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
Abstract: an integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. a first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.
Inventor(s): Charles Chew-Yuen YOUNG of Cupertino CA (US) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ming LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shun-Li CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kam-Tou SIO of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Kuang CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ru-Gun LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, G06F30/394, H01L21/768, H01L21/8234, H01L23/485
Abstract: a semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. the semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. the first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
20240096873.ESD STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chun-Chia HSU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Heng HSIEH of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Feng CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Bao-Ru YOUNG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Jam-Wem LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hung WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L29/06, H01L29/861
Abstract: electrostatic discharge (esd) structures are provided. an esd structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. the semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. a first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. a second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. a third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. a fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. the oxide diffusion region is disposed between the first and second conductive features.
Inventor(s): Mao-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Ni Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lung-Kun Chu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Wei Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/786
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. a second channel structure is configured to transport charge carriers within a second transistor device. a second gate electrode layer wraps around the second channel structure. the second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. a third channel structure is configured to transport charge carriers within a third transistor device. a third gate electrode layer wraps around the third channel structure. the third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.
Inventor(s): Hsiao-Han LIU of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/78
Abstract: a semiconductor structures and a method for forming the same are provided. the semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. a left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. the semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. a left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. in addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.
Inventor(s): Ji-Cheng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hang Chiu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/28, H01L21/285, H01L21/762, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/51, H01L29/66
Abstract: a method of manufacturing a gate structure includes at least the following steps. a gate dielectric layer is formed. a work function layer is deposited on the gate dielectric layer. a barrier layer is formed on the work function layer. a metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. the barrier layer is formed by at least the following steps. a first tin layer is formed on the work function layer. a top portion of the first tin layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. a second tin layer is formed on the trapping layer.
Inventor(s): Yu-Shao CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chui-Ya PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kung-Wei LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Yeu TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/28, H01L21/311, H01L21/3205, H01L21/8222, H01L21/8238, H01L27/06, H01L29/66, H01L29/78, H10B10/00
Abstract: a method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. the method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. the method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.
Inventor(s): Kuo-Cheng Ching of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Hung Hsu of Miaoli (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L21/84, H01L27/12, H01L29/10, H01L29/423, H01L29/66, H01L29/775, H01L29/78
Abstract: an integrated circuit (ic) device comprises a substrate having a metal-oxide-semiconductor (mos) region; a gate region disposed over the substrate and in the mos region; and source/drain features in the mos region and separated by the gate region. the gate region includes a fin structure and a nanowire over the fin structure. the nanowire extends from the source feature to the drain feature.
Inventor(s): Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/417, H01L29/66, H01L29/78
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a first fin structure disposed at a first device region and extending from a substrate along a first direction, wherein the first fin structure comprises a first recess formed in a top of the first fin structure, the first recess having a bottom and a sidewall extending upwardly from the bottom, wherein the sidewall has a tapering profile. the structure also includes a first source/drain feature in contact with the first fin structure, and a first gate structure disposed in the first recess, the first gate structure extending along a second direction perpendicular to the first direction, wherein the first gate structure has a first gate dielectric layer, and the first gate dielectric layer has a sidewall surface and a bottom surface in contact with the sidewall and the bottom of the first recess, respectively.
Inventor(s): Jui-Chien Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Cheng Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Zhi-Chang Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Hung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lo-Heng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
Abstract: according to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. a width of the inner spacers differs between different layers of the fin stack.
Inventor(s): Po-Kang Ho of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Tsai-Yu Huang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
Abstract: in an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.
Inventor(s): Hao-Lin Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Jui Wang of Kaohsiung County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yuang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: a device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. the first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. the second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. the third substrate includes a plurality of photodiodes and a first transistor. the second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.
Inventor(s): Yan-Jhih HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Yuan HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Hsieh LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01G4/08, H01L23/522
Abstract: a method of making a semiconductor device includes forming a circuit layer over a substrate. the method further includes depositing an insulator over the substrate. the method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. the method further includes filling the test line trench to define a test line electrically connected to the circuit layer. the method further includes filling the first trench and the second trench to define a capacitor.
Inventor(s): Yu JIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Lee-Chuan TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/3065
Abstract: some implementations described herein include a deep trench capacitor structure and methods of formation. the deep trench capacitor structure may penetrate vertically into a silicon substrate. in some implementations, formation of the deep trench capacitor structure includes forming segments of a deep trench capacitor recess using a combination of in-situ oxidation/nitridation, ex-situ deposition, and reactive ion etching techniques. by forming the deep trench capacitor recess using the in-situ oxidation/nitridation operation, the ex-situ deposition, and the reactive ion etching techniques, a deep trench capacitor structure may be formed that meets target critical dimensions and has an aspect ratio of approximately 50:1.
Inventor(s): Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/78
Abstract: semiconductor structures and the manufacturing method thereof are disclosed. an exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.
Inventor(s): Chia-Ta Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Chiu Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/762, H01L27/088, H01L29/66, H01L29/78
Abstract: a semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.
Inventor(s): Jung-Chi Tai of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Horng Li of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Ren Jeng of Chu-Bei (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ru Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yan-Ting Lin of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yun Chin of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L21/762, H01L29/165, H01L29/66, H01L29/78
Abstract: an embodiment is a semiconductor structure. the semiconductor structure includes a fin on a substrate. a gate structure is over the fin. a source/drain is in the fin proximate the gate structure. the source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. the supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.
Inventor(s): Shih-Chuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tien-Lu LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Chuan YOU of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/08, H01L21/768, H01L29/66, H01L29/78
Abstract: a contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. the contact stack excludes a metal nitride layer in direct contact with the silicide layer.
Inventor(s): Xusheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Miao LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Keung LEUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Huiling SHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Youbo LIN of Ridgefield CT (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/40, H01L21/283, H01L21/285, H01L21/768, H01L29/45, H01L29/66
Abstract: a method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. an insulating layer (e.g., cesl, ild) is formed over the source/drain feature. a trench is etched in the insulating layer to expose a surface of the source/drain feature. a semiconductor material is then formed in the etched trench on the surface of the source/drain feature. the semiconductor material is converted to a silicide.
Inventor(s): Shih-Yen LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Cheng TSAI of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L21/8234, H01L29/04, H01L29/22
Abstract: a method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-d material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-d material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-d material layer exposed by the source/drain contacts, while leaving a second portion of the 2-d material layer remaining over the gate dielectric layer as a channel region.
Inventor(s): Wang-Chun HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L21/28, H01L21/285, H01L29/06, H01L29/08, H01L29/40, H01L29/423, H01L29/49, H01L29/66, H01L29/775
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a fin structure protruding from a substrate. the fin structure includes alternately stacked first semiconductor material layers and second semiconductor material layers. the method includes forming a spacer layer over the fin structure. the method includes forming a first inter-layer dielectric (ild) layer over the spacer layer. the method also includes recessing the fin structure and the first ild layer to form a first opening through the first ild layer. the method further includes forming an epitaxial structure in the first opening, and forming a second ild layer over the epitaxial structure and the first ild layer. in addition, the method includes removing the first semiconductor material layers, and forming a gate structure around the second semiconductor material layers.
Inventor(s): I-Wen WU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ming LEE of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/40, H01L29/66
Abstract: methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. the dummy layer and subsequent air gap may be formed after a sac dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.
Inventor(s): Chung-Ting LI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Hsiang LU of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/49, H01L29/66, H01L29/78
Abstract: a method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. the first gate spacer is between the second gate spacer and the first gate structure. a first interlayer dielectric (ild) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. a portion of the second gate spacer and a portion of the first ild layer are removed simultaneously. a top surface of the second gate spacer is lower than a top surface of the first ild layer.
Inventor(s): Shen-Yang Lee of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/66, H01L29/786
Abstract: a method for tuning a threshold voltage of a transistor is disclosed. a channel layer is formed over a substrate. an interfacial layer is formed over and surrounds the channel layer. a gate dielectric layer is formed over and surrounds the interfacial layer. a dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. a thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.
Inventor(s): Lung-Kun CHU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Ni YU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mao-Lin HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/66, H01L29/775, H01L29/786
Abstract: a method for forming a semiconductor device is provided. the method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. the cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. the method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. the p-type work function metal layer merges in the second spaces.
Inventor(s): Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lo-Heng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66, H01L29/786
Abstract: a semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. the dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. the isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
Inventor(s): Po-Chin Chang of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Zhen Yu of New Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Yuting Cheng of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Li Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the structure includes a first source/drain region disposed in a pfet region and a second source/drain region disposed in an nfet region. the second source/drain region comprises a dipole region. the structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. the first, second, and third silicide layers include different materials. the structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.
Inventor(s): Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chij-chien CHI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ying LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsu-Kai CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chein-Shun LIAO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Keng-chu LIN of Ping-Tung (TW) for taiwan semiconductor manufacturing co., ltd., KAi-Ting HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/768, H01L23/532, H01L23/535, H01L29/78
Abstract: the present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. the method includes depositing a first dielectric on a substrate having a gate structure and source/drain (s/d) structures, forming an opening in the first dielectric to expose the s/d structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. the method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form s/d conductive structures with a top surface coplanar with a top surface of the first dielectric.
Inventor(s): Kai-Di Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ming Lee of Yangmei (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Chu-Pei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/8238, H01L27/092, H01L29/40, H01L29/417, H01L29/78
Abstract: a device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. the silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.
Inventor(s): Pei-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/02, H01L21/285, H01L21/311, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: a semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.
Inventor(s): Shih-Hang Chiu of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Jui-Yang Wu of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/28, H01L29/49
Abstract: disclosed is a semiconductor device and semiconductor fabrication method. a semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. a semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Uei Jang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/78
Abstract: a semiconductor device is described. an isolation region is disposed on the substrate. a plurality of channels extend through the isolation region from the substrate. the channels including an active channel and an inactive channel. a dummy fin is disposed on the isolation region and between the active channel and the inactive channel. an active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. a dielectric material extends through the active gate and contacts a top of the dummy fin. the inactive channel is a closest inactive channel to the dielectric material. a long axis of the active channel extends in a first direction. a long axis of the active gate extends in a second direction. the active channel extends in a third direction from the substrate. the dielectric material is closer to the inactive channel than to the active channel.
Inventor(s): Chandrashekhar P. SAVANT of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tien-Wei YU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Chih LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ming TSAI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/40, H01L29/49, H01L29/78
Abstract: a semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. the channel region is over the substrate. the gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. the source/drain regions are at opposite sides of the channel region.
Inventor(s): Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chen Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Yu Lai of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ziwei Fang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/225, H01L21/265, H01L29/165
Abstract: doping techniques for fin-like field effect transistors (finfets) are disclosed herein. an exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. the doped amorphous layer includes a non-crystalline form of a material. in some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. in some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
Inventor(s): Han-Yu LIN of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Fang-Wei LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kai-Tak LAM of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Raghunath PUTIKAM of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tzer-Min SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd., Cheng-Tzu YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Li LEE of Yunlin County (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Chung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/78
Abstract: a method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an fgas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
Inventor(s): Chia-Ming PAN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ta HSIEH of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Wei LIU of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Chi WU of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L29/66
Abstract: a semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. the first to third isolation structures are over the semiconductor substrate and spaced apart from each other. the semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. the conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong CHIA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Martin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, G11C11/22, H01L29/66, H10B51/30
Abstract: a method (of writing to a ferroelectric field-effect transistor (fefet) configured as a 2-bit storage device that stores two bits, wherein the fefet includes a first source/drain (s/d) terminal, a second s/d terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first s/d terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second s/d terminal; and wherein the first source/drain voltage is lower than the gate voltage.
Inventor(s): Wei-Jen LAI of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming CHEN of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Lin LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/28, H01L21/762, H01L21/8238, H01L27/092, H01L29/06, H01L29/10, H01L29/49
Abstract: the present disclosure provides one embodiment of a method making semiconductor structure. the method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
Inventor(s): Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Chang of Chu-Bei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hsin Ko of Fongshan City (TW) for taiwan semiconductor manufacturing co., ltd., Feng Yuan of Yonghe City (TW) for taiwan semiconductor manufacturing co., ltd., Jeff J. Xu of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/306, H01L21/31, H01L21/311, H01L21/76, H01L29/06, H01L29/08, H01L29/165, H01L29/66
Abstract: a field effect transistor includes a substrate comprising a fin structure. the field effect transistor further includes an isolation structure in the substrate. the field effect transistor further includes a source/drain (s/d) recess cavity below a top surface of the substrate. the s/d recess cavity is between the fin structure and the isolation structure. the field effect transistor further includes a strained structure in the s/d recess cavity. the strain structure includes a lower portion. the lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. the strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
Inventor(s): Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing co., ltd., I-Wen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L27/12, H01L29/786
Abstract: epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (fets) or gate-all-around (gaa) fets, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. an exemplary device includes a dielectric substrate. the device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. the channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. the epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. the inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. in some embodiments, the outer portion physically contacts the dielectric substrate.
Inventor(s): Hsin-Hao Yeh of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Ting Yen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/324, H01L21/762, H01L29/66
Abstract: a method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
Inventor(s): Chien-Chang CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: the present disclosure describes a semiconductor device having a crystalline high-k dielectric layer. the semiconductor structure includes a fin structure on a substrate, a gate dielectric layer on the fin structure, and a gate structure on the gate dielectric layer. a top portion of the gate dielectric layer is crystalline and includes a crystalline high-k dielectric material.
Inventor(s): Neil Quinn Murray of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Wei Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mauricio MANFRINI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L21/8258, H01L27/12, H01L29/66
Abstract: a thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. the thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.
Inventor(s): Huaixin XIAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Ying LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Liu HAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Xiangdong CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037, G01R31/3177, G01R31/3185, H03K19/00, H03K19/0948
Abstract: a scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second i/o nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first i/o node, and a second driver coupled between the flip-flop circuit and the second i/o node. the selection circuit and drivers receive a scan direction signal. in response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. in response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
20240097662.INPUT BUFFER CIRCUIT_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yu-Kai TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037, H03K3/13, H03K3/3565
Abstract: an integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. in the control circuit, a first switch is electrically connected to a second switch at a buffer output node. the control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.
Inventor(s): Kai-Hsuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ta Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yu Yang of Xihu Township (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, H01L21/027, H01L21/306, H01L21/311, H01L21/8234, H01L21/8238, H01L27/092, H01L29/08, H01L29/66
Abstract: a method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. the first and the second semiconductor fins have a first distance. a third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. the third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. an epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. the first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
Inventor(s): YU-KUAN LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., CHANG-TA YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., PING-WEI WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., KUO-YI CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., MEI-YUN WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, G11C11/412, H01L21/768, H01L23/522, H01L27/02, H01L29/66
Abstract: an integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. the first transistor includes a channel region, a source region and a drain region. a conductive contact is coupled to the drain region of the first transistor. a second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. the gate of the second transistor is spaced from the gate of the first transistor. a conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. an expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
Inventor(s): Chien-Ying CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B20/20, G06F30/392
Abstract: a method of generating an integrated circuit (ic) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (otp) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.
Inventor(s): Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B43/27, H01L23/532, H10B43/20
Abstract: memory devices and methods of forming the same are provided. a memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. the stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending bet ween the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. the first and second silicide layers include cobalt, titanium, tungsten, or palladium.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/30
Abstract: a memory structure includes a plurality of memory cells arranged in an array. each of the memory cells includes a memory region, a word line portion disposed on a first surface of the memory region, a first conductive block disposed on a second surface of the memory region opposite to the first surface, a second conductive block disposed on the second surface of the memory region, and a third conductive block disposed on the second surface of the memory region such that the third conductive block is disposed between and separated from the first conductive block and the second conductive block.
Inventor(s): Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Ting Sung of Yangmei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B63/10
Abstract: various embodiments of the present application are directed toward an integrated chip (ic). the ic comprises a dielectric structure disposed over a substrate. a phase change material (pcm) structure is disposed over the dielectric structure. a first conductive structure and a second conductive structure are disposed over and electrically coupled to the pcm structure. a heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. the heating structure has a first surface and a second surface opposite the first surface. the first surface faces the pcm structure. the first surface has a first width and the second surface has a second width that is greater than the first width.
Inventor(s): Meng-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B63/00, G11C13/00, H01L21/28, H01L29/423
Abstract: a semiconductor device includes a first transistor, a second transistor, and a memory component. the first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. the second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. the memory component is above the first and second transistors, and electrically coupled to the second source or drain region.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong CHIA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chenchen Jacob WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B63/00, G11C13/00, H10N70/00, H10N70/20
Abstract: a memory device includes at least one bit line, at least one word line, at least one memory cell, at least one source line, and a controller electrically coupled to the at least one memory cell via the at least one word line, the at least one bit line, and the at least one source line. the memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. the first transistor includes a gate electrically coupled to the word line, and first and second source/drains. each data storage element and the corresponding second transistor are electrically coupled in series with the first source/drain of the first transistor and the bit line. the controller controllably applies a voltage other than a ground voltage to the at least one source line in an operation of a selected data storage element among the data storage elements.
Inventor(s): Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing co., ltd., You-Ru Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yan-Jie Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N39/00, H10N30/074, H10N30/20
Abstract: in some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. during the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. the second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.
Inventor(s): Yu-Feng Yin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Min-Kun Dai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hua Huang of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/01, G11C11/16, H01L21/768, H01L23/522, H10B61/00, H10N50/80, H10N50/85
Abstract: semiconductor structure and methods of forming the same are provided. an exemplary method includes receiving a workpiece including a magnetic tunneling junction (mtj) and a conductive capping layer disposed on the mtj, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. the method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
Inventor(s): Tai-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Shu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sin-Yi Yang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Jung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien Chung Huang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Ting Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jyu-Horng Shieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Qiang Fu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/01, H10N50/80
Abstract: a method includes forming magnetic tunnel junction (mtj) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. the method further includes patterning the mtj stack layers to form a mtj; and performing a passivation process on a sidewall of the mtj to form a protection layer. the passivation process includes reacting sidewall surface portions of the mtj with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
Inventor(s): Yi Yang of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd., Dongna Shen of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Yu-Jen Wang of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/01, H01F10/32, H01F41/34, H10N50/10, H10N50/80
Abstract: a first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. the conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. a second conductive layer is deposited over the first dielectric layer and the conductive via. the second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a t-shaped second bottom electrode. mtj stacks are deposited on the t-shaped second bottom electrode and on the first bottom electrode wherein the mtj stacks are discontinuous. a second dielectric layer is deposited over the mtj stacks and planarized to expose a top surface of the mtj stack on the t-shaped second bottom electrode. a top electrode contacts the mtj stack on the t-shaped second bottom electrode plug.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 21st, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- C23C14/35
- C23C14/00
- C23C14/04
- C23C14/06
- C23C14/22
- C23C14/34
- C23C16/04
- C23C16/34
- C23C16/455
- H01J37/34
- H01L21/02
- H01L21/285
- H01L21/67
- H01L21/768
- Taiwan semiconductor manufacturing co., ltd.
- G01R31/28
- G01R31/317
- G06F30/398
- H01L21/66
- H01L23/00
- H01L23/12
- H01L23/498
- G02B6/122
- G02B6/13
- G02B6/136
- G02B6/132
- G02B6/12
- H01L23/48
- H01L25/16
- G03F1/44
- G03F1/42
- G03F1/84
- G03F1/62
- B82Y30/00
- H01L21/027
- G03F1/64
- G06F3/06
- G06F30/3308
- G06F30/39
- G06F30/392
- G06F30/394
- H01L29/40
- G03F1/36
- G11C7/10
- G11C5/06
- G11C8/08
- G11C8/10
- G11C11/22
- H10B51/30
- G11C11/4091
- G11C11/4093
- G11C11/4094
- G11C17/18
- G11C17/16
- C23C14/18
- C23C14/54
- H01J37/32
- G03F7/004
- G03F7/075
- G03F7/16
- H01L21/308
- H01L21/311
- H01L21/3213
- H01L21/033
- H01L21/28
- H10B41/35
- H10B41/43
- H01L29/49
- H01L29/66
- H01L29/78
- H01L21/321
- H01L21/56
- H01L23/31
- H01L25/00
- H01L25/10
- H01L21/8234
- H01L27/088
- H01L21/48
- H01L21/8249
- H01L23/522
- H01L23/538
- H01L21/68
- G06T1/00
- G06T7/00
- G06T7/73
- H01L23/544
- H01L21/8238
- H01L23/485
- H01L23/532
- H01L23/535
- H01L27/092
- H01L29/417
- H01L29/423
- H01L29/786
- H01L29/08
- H01L21/84
- H01L27/12
- H01L23/04
- H01L21/52
- H01L25/065
- H01L23/367
- H01L23/373
- H01L23/433
- H10B80/00
- H01L23/38
- H10N10/82
- H01L21/762
- G11C11/418
- H10B10/00
- H01L23/495
- H01L21/683
- H01L27/146
- H01L23/525
- H01L23/528
- H01L29/06
- H01L25/18
- H01L25/04
- H01L21/304
- H01L27/02
- H01L29/775
- H01L29/861
- H01L29/51
- H01L21/3205
- H01L21/8222
- H01L27/06
- H01L29/10
- H01G4/08
- H01L21/3065
- H01L29/165
- H01L21/283
- H01L29/45
- H01L29/04
- H01L29/22
- H01L21/225
- H01L21/265
- H01L21/306
- H01L21/31
- H01L21/76
- H01L21/324
- H01L21/8258
- H03K3/037
- G01R31/3177
- G01R31/3185
- H03K19/00
- H03K19/0948
- H03K3/13
- H03K3/3565
- G11C11/412
- H10B20/20
- H10B43/27
- H10B43/20
- H10B63/10
- H10B63/00
- G11C13/00
- H10N70/00
- H10N70/20
- H10N39/00
- H10N30/074
- H10N30/20
- H10N50/01
- G11C11/16
- H10B61/00
- H10N50/80
- H10N50/85
- H01F10/32
- H01F41/34
- H10N50/10
