Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 29th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on February 29th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 93 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L23/00 (24), H01L21/56 (19), H01L29/66 (17), H01L23/31 (16), H01L23/538 (16)
With keywords such as: layer, structure, semiconductor, gate, device, region, die, substrate, source, and disposed in patent application abstracts.
See the following report for Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on February 29th, 2024:
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 29th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Chia-Ling PAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B08B7/04, B08B3/04, B08B3/08, B08B5/02, B08B7/02, H01L21/02
Abstract: a method of cleaning wafer-cleaning brushes includes passing a wafer having a first polished main side and an opposing unpolished backside between a pair of substantially cylindrical shaped wafer-cleaning brushes are rotated about an axial direction of the brushes while passing the wafer between the pair of wafer-cleaning brushes. a cleaning solution is applied to the brushes while passing the wafer between the pair of wafer-cleaning brushes. while passing between the pair of brushes, the first polished main side of the wafer faces a first direction, the first direction is an opposite direction to which a polished side of a production wafer faces during a subsequent polished wafer cleaning operation. the substantially cylindrical shaped wafer-cleaning brushes include a plurality of protrusions on an external surface of the brushes, and the brushes contact the wafer at least a portion of time the wafer is passing between the pair of brushes.
Inventor(s): Nai-Han CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Piao Hsu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N21/95, G01N21/33
Abstract: in an embodiment, a system includes: a broadband light source; a wafer with a first side facing the broadband light source; a first light sensor configured to detect reflected light from the broadband light source emanating from the first side; a second light sensor configured to detect emergent light emanating from a second side of the wafer opposite the first side, wherein the emergent light originates from the broadband light source; and a detector module configured to analyze the reflected light and the emergent light to identify wafer defects.
Inventor(s): Beih-Tzun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng Yuan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/13
Abstract: a method of wavelength tuning in a silicon photonics circuit includes receiving a bus waveguide, a ring resonator optically coupled to the bus waveguide, and a dielectric layer over the bus waveguide and over the ring resonator. the method further includes performing a first heat process at a first temperature to heat up the dielectric layer, where the first heat process shifts an initial resonance wavelength of the ring resonator to a first resonance wavelength shorter than the initial resonance wavelength. the first heat process permanently shifts the initial resonance wavelength to the first resonance wavelength, the first resonance wavelength being a wavelength when no heat is being applied to the ring resonator.
Inventor(s): Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hsiang Hsu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ming Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/34, G02B6/42, H01L21/56, H01L25/065
Abstract: a semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. the first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. the insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. the redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. the at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die. the at least one reflector is disposed on the at least one prism structure.
Inventor(s): Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/132, G02B6/136
Abstract: a semiconductor structure including a semiconductor waveguide layer over a second dielectric layer and between sidewalls of a first dielectric layer. a first cladding layer is between the sidewalls of the first dielectric layer and directly over the semiconductor waveguide layer. a second cladding layer is between sidewalls of the second dielectric layer and directly under the semiconductor waveguide layer. a difference between a refractive index of the semiconductor waveguide layer and a refractive index of the first cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the first dielectric layer. a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second dielectric layer.
Inventor(s): Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei TSENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, G02B6/293
Abstract: a package structure comprises photonic dies and an interposer structure. each photonic die includes a dielectric layer and a first grating coupler embedded in the dielectric layer. the interposer structure is disposed below the photonic dies. the interposer structure includes an oxide layer and a second grating coupler embedded in the oxide layer. the photonic dies are optically coupled through the first grating couplers of the photonic dies and the second grating coupler of the interposer structure.
Inventor(s): Ting-Pi SUN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/22
Abstract: in a method of manufacturing a pellicle for an extreme ultraviolet (euv) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.
Inventor(s): Wei-Che HSIEH of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Cheng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Hsun Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng Lien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/32
Abstract: in a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. the mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. the intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. the intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.
Inventor(s): Hung-Chih HSIEH of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
Abstract: a method of overlay error measurement includes disposing a reference pattern module over a substrate. the substrate includes first and second overlay measurement patterns in first and second locations. the reference pattern module includes first and second reference patterns. the method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. the method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. the method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.
Inventor(s): Xiaoyu SUN of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Xiaochen PENG of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Murat Kerem AKARVARDAR of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F9/50, G06F7/50, G06F15/80
Abstract: an artificial intelligence (ai) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (pe) array. each mini buffer is associated with a subset of rows or a subset of columns of the pe array. partitioning an on-chip buffer of the ai accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. the reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the ai accelerator device. this may increase the operating efficiency and/or may increase the performance of the ai accelerator device. moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the pe array.
Inventor(s): Johnny Chiahao LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xiangdong CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/394
Abstract: an integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. the integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. the first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.
Inventor(s): Hua-Hsin YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hung LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Tai SHIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06
Abstract: a device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. the input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. the switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. the first latch circuit is coupled to the switching circuit by the first data line and the second data line. the first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.
Inventor(s): Min-Chiao YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ji Kuan LEE of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/12, G11C13/00
Abstract: a method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.
Inventor(s): Perng-Fei Yuh of Walnut Creek CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22, G11C11/56, H10B51/00
Abstract: a memory device includes a plurality of memory cells. each memory cell includes a multi-gate fefet that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching e-field.
Inventor(s): Tzu-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi Tu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Shiuan Tsair of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22, H01L29/51, H10B51/30, H10B51/40
Abstract: the present disclosure relates to an integrated chip structure. the integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. a select gate is over the substrate between the first source/drain region and the second source/drain region. a ferroelectric random access memory (feram) device is over the substrate between the select gate and the first source/drain region. a transistor device is disposed on an upper surface of the substrate. the substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. the feram device is arranged over the recessed surface.
Inventor(s): He-Zhou WAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Xiu-Li YANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Mu-Yang YE of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Yan-Bo SONG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/408, G11C5/06, G11C11/4074, G11C11/4094
Abstract: a memory device includes a first transistor, a second transistor and a third transistor. the first transistor is coupled to a first word line at a first node. the second transistor is coupled to a second word line different from the first word line at a second node. a control terminal of the first transistor is coupled to a control terminal of the second transistor. the third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. in a layout view, each of the first transistor and the second transistor has a first length along a direction. the first transistor, the third transistor and second transistor are arranged in order along the direction. a method is also disclosed herein.
Inventor(s): Sanjeev Kumar Jain of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/418
Abstract: systems and methods are provided for a memory device. a memory device includes a memory array, a column selection circuit coupled to the memory array, where the column selection circuit is configured to generate a column selection signal, and a sense amplifier configured to receive data signals from the memory array. an enable signal generating circuit is configured to generate a first enable signal and a second enable signal. the column selection circuit generates the column selection signal based on the first enable signal, and the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.
Inventor(s): Pei-Chun LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kai CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/08, G11C16/26, G11C16/32
Abstract: a memory device is provided, including a memory array, a driver circuit, and recover circuit. the memory array includes multiple memory cells. each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. the driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. the recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. the third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Min-Shin Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/16, G11C11/4074, G11C11/408, G11C11/4094, G11C11/56
Abstract: a memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
Inventor(s): Sheng-Liang Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bing-Hung Chen of San-Xia Town (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yang Hung of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jyu-Horng Shieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Huei Suen of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Syun-Ming Jang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jack Kuo-Ping Kuo of Pleasanton CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, H01L21/02, H01L21/311, H01L21/321
Abstract: embodiments described herein relate to plasma processes. a plasma process includes generating a plasma containing negatively charged oxygen ions. a substrate is exposed to the plasma. the substrate is disposed on a pedestal while being exposed to the plasma. while exposing the substrate to the plasma, a negative direct current (dc) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.
Inventor(s): Hsueh-Ju Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Da Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei Ying Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Hsu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/311, H01L29/40, H01L29/49, H01L29/66
Abstract: a method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. the first treatment process is performed using a fluorine-containing gas. a first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. the method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. after the second drive-in process, conductive layers are formed to fill the trench.
Inventor(s): Guancyun Li of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng Tung of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, H01L21/67
Abstract: an apparatus in an overhead transport system is provided. the apparatus includes a hanger feature configured to be hung from a ceiling, a plate-like structure having a top surface and a bottom surface, the bottom surface being rotatably coupled to the hanger feature, and at least one pair of rail members mechanically coupled to the bottom surface of the plate-like structure by way of a plurality of yoke members.
Inventor(s): Chung-Lei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Anhao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-I Kang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/84
Abstract: a method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. the method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. the method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. the un-implanted region is retained to form a pillar under the epitaxial layer. next, an insulating material is disposed in the cavity and the trench. the method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.
Inventor(s): Tzu-Yu Lin of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L23/532, H01L27/06, H01L27/105
Abstract: a dielectric structure is formed over a layer than contains a conductive component. an opening is formed in the dielectric structure. the opening exposes an upper surface of the conductive component. a first deposition process is performed that deposits a first conductive layer over the dielectric structure and partially in the opening. a treatment process is performed on a first portion of the first conductive layer formed over the dielectric structure. the treatment process introduces a non-metal material to the first portion of the first conductive layer. after the treatment process has been performed, a second deposition process is performed that at least partially fills the opening with a second conductive layer without trapping a gap therein.
Inventor(s): Zi-Jheng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Cheng Kuo of Shin-Chu county (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/56, H01L21/78, H01L23/31, H01L23/532, H01L23/538
Abstract: a method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. the formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. a development process is then performed and a dual damascene opening is formed in the dielectric material layer. a seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. a metal layer is formed over the seed metallic layer. a redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
Inventor(s): Chun-Kai Chen of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Jei Ming Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/311
Abstract: a method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. a first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. a second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. the second width is less than the first width. the first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.
Inventor(s): Chin-Lung CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Tang HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Wei LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532
Abstract: a method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Ling Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Wei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/77, H01L23/00, H01L23/528, H01L25/18
Abstract: systems, devices and methods of manufacturing a system on silicon wafer (sosw) device and package are described herein. a plurality of functional dies is formed in a silicon wafer. different sets of masks are used to form different types of the functional dies in the silicon wafer. a first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. a second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. an optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. the optional backside redistribution structure may provide backside interconnects between functional dies of different types.
Inventor(s): Chi-Wei WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya YEH of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/762, H01L27/11
Abstract: a method for forming a semiconductor structure is provided. the method for forming the semiconductor structure includes forming first fin structures and a second fin structures over a substrate, forming a first gate stack and a second gate stack that extend in a first direction across the first fin structures and the second fin structures, respectively, and etching the first gate stack and the second gate stack to form a first trench through the first gate stack and a second trench through the second gate stack. a first dimension of the first trench in the first direction is greater than a second dimension of the second trench in the first direction. the method further includes forming a first gate cutting structure and a second gate cutting structure in the first trench and the second trench, respectively.
Inventor(s): Chia-Chu LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-He LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yun WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device includes a semiconductor substrate, an isolation feature, gate lines, and a first gate structure. the isolation feature is over the semiconductor substrate and surrounding an active region of the semiconductor substrate. the gate lines extend across the active region of the semiconductor substrate. the first gate structure is over the isolation feature. the first gate structure comprises a first gate line, a second gate line, and a first bridge portion, the first and second gate lines are substantially parallel with the gate lines, and the first bridge portion connects the first gate line to the second gate line.
Inventor(s): Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chih Yuan of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Scott Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hao Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Wei Chou of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/66
Abstract: the present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. the semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (hfd) region. a gate electrode is disposed above the hfd region and the hfd region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.
Inventor(s): Hung-Li CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Sheng CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lei-Chun CHOU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/66, H01L29/78
Abstract: a method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. an electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. a gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
Inventor(s): Chun-Fai CHENG of Tin Shui Wai (HK) for taiwan semiconductor manufacturing company, ltd., Chang-Miao LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chung CHEN of Taipei City 111 (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/28, H01L21/311, H01L21/3115, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/51, H01L29/66, H01L29/786
Abstract: a semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. the method includes depositing a high-k dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (rem)-based dopant on first and second portions of the high-k dielectric layer, and performing a second doping with the rem-based dopants on the first portions of the high-k dielectric layer and third portions of the high-k dielectric layer. the first doping dopes the first and second portions of the high-k dielectric layer with a first rem-based dopant concentration. the second doping dopes the first and third portions of the high-k dielectric layer with a second rem-based dopant concentration different from the first rem-based dopant concentration. the method further includes depositing a work function metal layer on the high-k dielectric layer and depositing a metal fill layer on the work function metal layer
Inventor(s): Yi-Huan Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Yin Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pu Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/10, H01L21/52, H01L21/56, H01L23/00, H01L23/16, H01L23/31, H01L23/367, H01L23/538
Abstract: a semiconductor package including two different adhesives and a method of forming are provided. the semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. the first adhesive may encircle the package component and the heat transfer layer. the lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. a material of the second adhesive may be different from a material of the first adhesive.
Inventor(s): Jian-You Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chung Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsuan Tsai of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Kung-Chen Yeh of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Ju Tsou of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/16, H01L21/48, H01L21/56, H01L23/31, H01L23/498
Abstract: a semiconductor package including one or more dam structures and the method of forming are provided. a semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. the one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. the coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.
Inventor(s): Wen-Yi LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Chun LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Li KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chio LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/373, H01L23/538, H01L25/00, H01L25/18
Abstract: some implementations described herein a provide a multi-die package and methods of formation. the multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. the heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. the heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
20240071855.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/18
Abstract: a package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. the semiconductor die laterally encapsulated by an insulating encapsulation. the redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. the redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. the backside dielectric layer is disposed on the redistribution circuit structure. the conductive terminals penetrate through the backside dielectric layer. the electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals. the underfill is disposed between the backside dielectric layer and the electronic device, wherein the underfill is thermally coupled to the thermal enhancement structures.
Inventor(s): Chih-Chien Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/498, H01L23/538, H01L25/16
Abstract: a semiconductor device includes a package substrate, a package component and at least one adhesive pattern. the package component has a thermal interface material (tim) layer thereon. the adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the tim layer.
Inventor(s): Xinyu Bao of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jyh Chwen Frank Lee of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sam Vaziri of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/42, H01L21/48, H01L21/56, H01L23/00, H01L23/29, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/10
Abstract: packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. in an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.
Inventor(s): Zi-Jheng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yang Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Tan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L25/16
Abstract: a semiconductor package includes a first die, a second die and a redistribution layer structure. the first die and the second die are disposed laterally. the redistribution layer structure is disposed over and electrically connected to the first die and the second die, wherein the redistribution layer structure includes a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers, and wherein from a top view, first vias of the plurality of vias overlapping with the first die or the second die have an elliptical-like shape.
20240071888.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chien-Chang Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Fu Su of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Liang Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yang Yu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L25/065
Abstract: a package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. the redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. the first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. the wiring substrate includes second conductive pads. the first conductive terminals are disposed between the first conductive pads and the second conductive pads. the insulating encapsulation is disposed on the surface of the redistribution circuit structure. the insulating encapsulation laterally encapsulates the wiring substrate.
Inventor(s): Yi-Wen WU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Techi WONG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao TSAI of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao CHUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ting HUNG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/528
Abstract: a semiconductor package is provided. the semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. the interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. the interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. the insulating features is arranged in a matrix and faces a top surface of the semiconductor die. the interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. the first conductive features surround the matrix of the insulating features.
Inventor(s): Harry-Haklay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tuo Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Feng Teng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/64, H01L25/065
Abstract: a semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. a method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
Inventor(s): Chia-Yu Ling of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/498, H01L25/16
Abstract: disclosed are an interposer substrate, a package structure and a manufacturing method of a package structure. in one embodiment, the interposer substrate includes a substrate, a bridge device in the substrate, a memory in the substrate and beside the bridge device and a through substrate via in the substrate and beside the bridge device and the memory.
Inventor(s): Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/31
Abstract: a semiconductor structure includes a composite redistribution structure, a first interconnect device and an integrated circuit (ic) package component. the composite redistribution structure includes a first redistribution structure, a second redistribution structure and a third redistribution structure. the second redistribution structure is located between the first redistribution structure and the third redistribution structure. the first interconnect device is embedded in the second redistribution structure. the first interconnect device includes a plurality of metal connectors leveled with a surface of the second redistribution structure and electrically connected to the third redistribution structure. the ic package component is disposed over the third redistribution structure and electrically connected to the first interconnect device via the third redistribution structure.
Inventor(s): Ming-Fa Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Han Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L25/065, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.
Inventor(s): Yu-Ling Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lai Wei Chih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Tsan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Han Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chia Chiu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hung Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/053, H01L25/18
Abstract: a semiconductor package including a ring structure with one or more indents and a method of forming are provided. the semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. the ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. the first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
Inventor(s): Chih-Chiang Tsao of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wei Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/00, H01L25/10
Abstract: a method includes depositing solder paste over first contact pads of a first package component. spring connectors of a second package component are aligned to the solder paste. the solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. a device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. each of the plurality of spring coils extends from the first package component to the second package component.
Inventor(s): Kai-Ming Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-wei Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lun Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Min Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Da Tsai of Chiayi Country (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Feng Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hao Chen of HsinChu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiang Chiu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/00, H01L25/065
Abstract: a memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. the conductive terminals are disposed on a first surface of the base semiconductor die. the memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. the insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. the buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. a package structure including the above- mentioned memory device is also provided.
20240071954.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Kai-Ming Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-wei Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lun Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Min Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Da Tsai of Chiayi Country (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Feng Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hao Chen of HsinChu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiang Chiu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/00, H01L25/065
Abstract: a memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. the conductive terminals are disposed on a first surface of the base semiconductor die. the memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. the insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. the buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. a package structure including the above-mentioned memory device is also provided.
Inventor(s): Chih Hsin YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yen Lian LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Nan WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L21/8234, H01L23/48, H01L23/58, H01L27/088
Abstract: semiconductor structures and methods for forming the same are provided. a method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. the via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/8238, H01L23/522, H01L27/02, H01L27/092
Abstract: an integrated circuit layout is provided. the integrated circuit layout includes: a first active region having a first plurality of field effect transistors (fets); and an interconnect contacting sources and drains of the first plurality of fets in the first active region through a first set of contact structures. at least one of the first set of contact structures is electrically non-conductive.
Inventor(s): Jun-De JIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L23/528, H01L27/088, H01L29/06, H01L29/417
Abstract: devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. in one example, a semiconductor device formed to serve as an antenna switch is disclosed. the semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. the substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. the at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
Inventor(s): Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Huang of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L21/48, H01L23/48
Abstract: a package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.
Inventor(s): Mao-Yen Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung Pan of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Cheng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Lai of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsuan Tai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/538, H01L25/00, H01L25/18
Abstract: a method of fabricating a semiconductor structure includes the following steps. a semiconductor wafer is provided. a plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. a first barrier structure is formed in between the second surface mount components and the semiconductor wafer. an underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
Inventor(s): Yi-Jung Chen of Yilan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu Tsai of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: in an embodiment, a device bonding apparatus is provided. the device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.
Inventor(s): Tseng Hsing Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Hsin-chu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chi Lin of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-An Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Cheng Wu of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/66, H01L23/00, H01L23/31, H01L23/498, H01L23/538
Abstract: a first polymer layer is formed across a package region and a test region. a first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. the first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. a second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. the second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.
Inventor(s): Wei-Yu Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hsien Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shih Yeh of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Wei Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/56, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H01L25/00
Abstract: a package structure and the manufacturing method thereof are provided. the package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. the through insulator vias are encapsulated in the insulating encapsulation. the first package and the second package are electrically connected through the solder joints. a maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
Inventor(s): Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L23/00, H01L23/31, H01L23/538, H01L25/00
Abstract: a semiconductor package includes a first redistribution structure, a second redistribution structure, a first die, a first encapsulant, a second die, a second encapsulant, conductive connectors, and a third die. the second redistribution structure is over the first redistribution structure. the first die is located between the first redistribution structure and the second redistribution structure. the first encapsulant laterally encapsulates the first die. the second die is disposed on and electrically connected to the second redistribution structure. the second encapsulant laterally encapsulates the second die. the conductive connectors surround the second die and are embedded in the second encapsulant. the third die is disposed over the second die. the third die is in physical contact with the second encapsulant and the conductive connectors.
Inventor(s): Ching-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chu Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/367, H01L25/065, H10B80/00
Abstract: a method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. the redistribution structure is electrically connected to the first device die through the through-via in the second device die. a supporting substrate is bonded to the first device die.
Inventor(s): Cheng-Ting CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin CAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/40, H01L29/423, H01L29/786
Abstract: a semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. the gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. the electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. methods for manufacturing the semiconductor structure are also disclosed.
Inventor(s): I-Shan Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
Abstract: the present disclosure provides a semiconductor structure in accordance with some embodiment. the semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region, first transistors that include first gate stacks disposed in the first circuit region, second transistors that include second gate stacks disposed in the second circuit region, and a guard ring structure disposed between the first circuit region and the second circuit region. the first gate stacks and the second gate stacks have different material compositions. the guard ring structure fully surrounds the second circuit region.
Inventor(s): Cheng-Ting Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Bo Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin Cai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238
Abstract: in an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.
Inventor(s): Chien-Te TU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/66, H01L29/775
Abstract: a device comprises a first semiconductor layer, a dielectric layer, a second semiconductor layer, and a gate structure. the first semiconductor layer is over a substrate. the first semiconductor layer comprises a first channel region and first source/drain regions on opposite sides of the first channel region. the dielectric layer is over the first semiconductor layer. the second semiconductor layer is over the dielectric layer. the second semiconductor layer comprises a second channel region and second source/drain regions on opposite sides of the second channel region. the gate structure comprises a first portion extending in the dielectric layer, a second portion wrapping around the first channel region of the first semiconductor layer, and a third portion wrapping around the second channel region of the second semiconductor layer.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Wei Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/08, H01L29/40, H01L29/417, H01L29/66, H01L29/78
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a substrate comprising an nmos region and a pmos region abutting the nmos region, a first shallow trench isolation (sti) disposed across the pmos region and the nmos region, the first sti has a first bottom being slanted from the nmos region towards the pmos region. the semiconductor device structure also includes a first fin disposed in the pmos region, a first source/drain epitaxial feature disposed over the first fin, a second fin disposed in the nmos region, a second source/drain epitaxial feature disposed over the second fin, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, the first dielectric feature having a portion embedded in the first sti. the semiconductor device structure further includes a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.
Inventor(s): Yu-Hung CHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui WANG of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching I. LI of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: a boron (b) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. the recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. the passivation layer may be formed in the recess by epitaxial growth. the use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.
Inventor(s): Chi-Hsien Chung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsuan Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L23/00
Abstract: various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (cmos) image sensor in which a pixel sensor spans multiple integrated circuit (ic) chips and is devoid of a shallow trench isolation (sti) structure at a photodetector of the pixel sensor. the photodetector and a first transistor form a first portion of the pixel sensor at a first ic chip. a plurality of second transistors forms a second portion of the pixel sensor at a second ic chip. by omitting the sti structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. hence, the doped well may consume less area of the photodetector. this, in turn, allows enhanced scaling down of the pixel sensor.
Inventor(s): Yi-Chen LO of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/08, H01L29/423, H01L29/66, H01L29/786
Abstract: various embodiments of the present disclosure provide a semiconductor device structure. in one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, an inner spacer disposed between two adjacent semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer, a gate spacer in contact with a portion of the gate dielectric layer. the semiconductor device structure further includes a first cap layer comprising a first portion disposed between and in contact with the source/drain feature and the gate spacer, and a second portion disposed between and in contact with gate spacer and the inner spacer.
Inventor(s): Wei-Xiang You of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-De Ho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Yang Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Yu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Hung Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Kan Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hua Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yun Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L23/528, H01L29/417, H01L29/423, H01L29/786
Abstract: a device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. the device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. the interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.
Inventor(s): Tsan-Chun Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Su-Hao Liu of Jhongpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/033, H01L21/285, H01L21/3115, H01L29/45
Abstract: a method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. the bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. the method further includes forming a silicide over the source/drain region after removing the bottom mask.
Inventor(s): Meng-Yu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu CHENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Hung HUANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/40, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. the first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. the first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. the second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. the metal rail extends in an x-direction and adjacent to the gate structure in a y-direction. the first source/drain contact and the second source/drain contact each has an l-shape in a y-z cross-sectional view. the first source/drain contact electrically connects the first source/drain feature to the metal rail. the second source/drain contact electrically connects the fourth source/drain feature to the metal rail.
Inventor(s): Li-Hui Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L27/02, H01L27/11, H01L27/12, H01L29/78
Abstract: a first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. the first gate has a first dimension measured in a first lateral direction. the first source/drain contact has a second dimension measured in the first lateral direction. a second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. the second gate has a third dimension measured in the first lateral direction. the second source/drain contact has a fourth dimension measured in the first lateral direction. a first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.
Inventor(s): Bo-Wen HSIEH of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsin CHAN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06
Abstract: a semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an isolation structure, and a gate structure. the first and second semiconductor fins extend upwards from a top surface of the semiconductor substrate. the isolation structure is between the first semiconductor fin and the second semiconductor fin. the gate structure includes a first work function layer, a second work function layer, and a third work function layer. the first work function layer surrounds the first semiconductor fin and the second semiconductor fin. the second work function layer surrounds the first semiconductor fin and is over the first work function layer. the third work function layer surrounds the first semiconductor fin and is over the second work function layer and the isolation structure. the first work function layer is in contact with the second work function layer and the third work function layer.
Inventor(s): Kuan-Ting Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/762, H01L29/06, H01L29/417, H01L29/51, H01L29/66, H01L29/786
Abstract: a semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. the shallow trench isolation structure is disposed over the substrate. the epitaxial structures are disposed over the shallow trench isolation structure. the one or more semiconductor channel layers connect the two epitaxial structures. the gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. the gate spacer is in contact with a sidewall of the gate metal layer. from a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.
Inventor(s): Tzu-Ging Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chang Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/786
Abstract: a semiconductor device includes a first channel region extending in a first lateral direction, and comprising a first epitaxial structure; a second channel region extends in the first lateral direction, next to the first channel region along a second lateral direction, and comprising a pair of second epitaxial structures; a third channel region formed over the substrate, extending in the first lateral direction, disposed next to the first channel region along the second lateral direction, and comprising a pair of third epitaxial structures; first and second metal gate structures extend in the second lateral direction and traverse the second and third channel regions, respectively. a first upper portion of the dielectric structure has its opposite sidewalls tilted away from each other along a vertical direction extending from a top surface of the dielectric structure toward the substrate.
Inventor(s): Kuo-Hua Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Je-Wei Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hua Feng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Huang Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Min-Yann Hsieh of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Java Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L21/768, H01L23/485, H01L29/08, H01L29/417, H01L29/45, H01L29/78
Abstract: a method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an inter-layer dielectric (ild). the dummy gate stack is in the ild, and the ild covers a source/drain region in the semiconductor region. the method further includes removing the dummy gate stack to form a trench in the first ild, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. a source region and a drain region are then formed on opposite sides of the metal gate.
Inventor(s): Chen-Huang Huang of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., An Chyi Wei of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Chih Wu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/311, H01L27/088, H01L29/06, H01L29/423, H01L29/49, H01L29/775, H01L29/786
Abstract: a semiconductor device structure and a manufacturing method thereof are provided. the semiconductor device structure includes a semiconductor substrate, semiconductor channel sheets disposed over the semiconductor substrate, and source and drain regions located beside the semiconductor channel sheets. a gate structure is disposed between the source and drain regions and disposed over the semiconductor channel sheets. the gate structure laterally surrounds the semiconductor channel sheets. the gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets. sidewall spacers are disposed between the gate structure and source and drain regions, and the sidewall spacers located next to the top gate electrode structure have slant sidewalls.
Inventor(s): Sung-Hsin Yang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chi Jeng of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Shang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Min Lin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Z.X. Fan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jung Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yu Kuo of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/08, H01L29/78
Abstract: a method of forming a finfet is disclosed. the method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. the method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.
Inventor(s): Marcus Johannes Henricus Van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/417, H01L29/66, H01L29/786
Abstract: a transistor includes a first gate electrode, a ferroelectric layer, a channel layer, a second gate electrode, and a hole supply layer. the ferroelectric layer is disposed over the first gate electrode. the channel layer is disposed on the ferroelectric layer. the second gate electrode is disposed over the channel layer. the hole supply layer is located between the second gate electrode and the channel layer. an electron trap density of the hole supply layer is higher than an electron trap density of the channel layer.
Inventor(s): Li-Wei Yin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Wen Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih-Ann Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia Ming Liang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66
Abstract: a semiconductor device is disclosed. the semiconductor device includes a semiconductor fin. the semiconductor device includes first spacers over the semiconductor fin. the semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. the semiconductor device includes a gate electrode contacting the metal gate structure. an interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.
Inventor(s): Wen-Shiang Liao of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01Q9/04, H01L21/48, H01L23/13, H01L23/498, H01L25/00, H01L25/065
Abstract: embodiments provide an integrated package device and method of forming the same, the device including a receive transmit integrated circuit die and embedded antenna. an oscillation region is aligned to the embedded antenna and a cavity is provided in the substrate to allow the passage of radio frequency (rf) signals into and out of the oscillation region.
Inventor(s): Wen-Shiang Liao of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01Q9/04, H01Q1/38, H01Q1/50
Abstract: embodiments provide an integrated package device and method of forming the same, the device having dual band functionality by way of a first antenna and a second antenna. the first antenna can transmit/receive high frequency radio frequency (rf) signals and the second antenna can transmit/receive lower frequency rf signals. a high-k dielectric zone is provided aligned to the first antenna. an oscillation region may be aligned to the embedded antenna(s).
Inventor(s): Nick Samra of Austin TX (US) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Ta-Pen Guo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/037, G01R31/317, G01R31/3177, G11C11/412, G11C11/419
Abstract: a flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. a bit write circuit is configured to receive a bit write signal. the received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. a hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
Inventor(s): Yangsyu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lung LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chi TIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chiting CHENG of Taiching City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, G11C11/419, H01L23/522, H01L23/528, H01L27/02, H01L27/092
Abstract: a static random access memory (sram) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an sram array. the sram periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. the second well region occupies a second distance in the row direction equal to the bitcell-pitch of the sram array. the second well region is disposed adjacent to the first well region in the row direction.
Inventor(s): Yun-Feng KAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia Yu LING of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/108
Abstract: a capacitorless dynamic random access memory (dram) cell may include a plurality of transistors. at least a subset of the transistors may include a channel layer that approximately resembles an inverted u shape, an ohm symbol (�) shape, or an uppercase/capital omega (�) shape. the particular shape of the channel layer provides an increased channel length for the subset of the transistors, which may reduce the off current and may reduce current leakage in the subset of the transistors. the reduced off current and reduced current leakage may increase data retention in the subset of the transistors and/or may increase the reliability of the subset of the transistors without increasing the footprint of the subset of the transistors. moreover, the particular shape of the channel layer enables the subset of the transistors to be formed with a top-gate structure, which provides low integration complexity with other transistors in the capacitorless dram cell.
Inventor(s): Chao-I Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H10B51/10
Abstract: a three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. the first stacking structure includes first stacking layers stacked along a vertical direction. each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. the second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. the first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.
Inventor(s): Meng-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/1159
Abstract: a semiconductor device includes a plurality of ferroelectric memory cells arranged over a substrate. each of the plurality of ferroelectric memory cells includes: a first conductive structure extending along a first lateral direction and having a central portion and a pair of side portions, the side portions respectively extending away from the central portion along a second lateral direction perpendicular to the first lateral direction; a ferroelectric layer disposed above the first conductive structure and in contact with the central portion of the first conductive structure; a channel film disposed above a portion of the ferroelectric layer; a second conductive structure disposed above and in contact with the channel film; and a third conductive structure disposed above and in contact with the channel film.
Inventor(s): Fu-Chen CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi TU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yu CHEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C11/22, H10B51/10, H10B53/00, H10B53/30
Abstract: a semiconductor device includes a random access memory (ram) structure and a dielectric layer. the ram structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. the dielectric layer is over the substrate and laterally surrounds a lower portion of the ram structure. from a cross-sectional view, the bottom electrode layer of the ram structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.
Inventor(s): Oreste Madia of Bruxelles (BE) for taiwan semiconductor manufacturing company, ltd., Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/16, H01L21/762, H01L23/528, H01L23/58, H01L27/092, H01L29/66, H01L29/78, H01L35/34
Abstract: a semiconductor structure includes a substrate, a device, a conductor, a backside interconnect, and a thermoelectric generator. the substrate has a front surface and a rear surface opposite to the front surface. the device is disposed on the front surface of the substrate. the conductor is disposed at or near the front surface of the substrate and electrically coupled to the device. the backside interconnect is disposed on the rear surface of the substrate and electrically coupled to the device. the thermoelectric generator is disposed in the substrate and electrically coupled to the device, and includes a first-type through via and a second-type through via. the first-type through via penetrates from the rear surface of the substrate to the conductor, and is connected to a first conductive feature of the backside interconnect and the conductor. the second-type through via penetrates from the rear surface of the substrate to the conductor, and is connected to a second conductive feature of the backside interconnect and the conductor. the second-type through via is different from the first-type through via.
Inventor(s): Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L45/00, H01L27/24
Abstract: a phase-change memory device and a method for fabricating the same are provided. the phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. the first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. the stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. the multi-layered spacer covers the stack. a first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.
Inventor(s): Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chun Chang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Feng Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L45/00, H01L27/24
Abstract: a memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. the phase change layer includes a gesbte material that contains a ge content of about 20 at % or less, a sb content of about 30 at % or more, and a te content of about 40 at % at or more.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 29th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B08B7/04
- B08B3/04
- B08B3/08
- B08B5/02
- B08B7/02
- H01L21/02
- Taiwan semiconductor manufacturing company, ltd.
- G01N21/95
- G01N21/33
- G02B6/12
- G02B6/13
- G02B6/34
- G02B6/42
- H01L21/56
- H01L25/065
- G02B6/122
- G02B6/132
- G02B6/136
- G02B6/293
- G03F1/22
- G03F1/32
- G03F7/00
- G06F9/50
- G06F7/50
- G06F15/80
- G06F30/392
- G06F30/394
- G11C7/06
- G11C7/12
- G11C13/00
- G11C11/22
- G11C11/56
- H10B51/00
- H01L29/51
- H10B51/30
- H10B51/40
- G11C11/408
- G11C5/06
- G11C11/4074
- G11C11/4094
- G11C11/419
- G11C11/418
- G11C16/08
- G11C16/26
- G11C16/32
- G11C17/16
- H01J37/32
- H01L21/311
- H01L21/321
- H01L21/28
- H01L29/40
- H01L29/49
- H01L29/66
- H01L21/677
- H01L21/67
- H01L21/762
- H01L21/84
- H01L21/768
- H01L23/522
- H01L23/528
- H01L23/532
- H01L27/06
- H01L27/105
- H01L21/78
- H01L23/31
- H01L23/538
- H01L21/77
- H01L23/00
- H01L25/18
- H01L21/8234
- H01L27/11
- H01L29/06
- H01L29/423
- H01L29/775
- H01L21/8238
- H01L27/092
- H01L29/78
- H01L21/3115
- H01L29/786
- H01L23/10
- H01L21/52
- H01L23/16
- H01L23/367
- H01L21/48
- H01L23/498
- H01L23/373
- H01L25/00
- H01L25/16
- H01L23/42
- H01L23/29
- H01L23/48
- H01L25/10
- H01L23/64
- H01L21/683
- H01L23/053
- H01L23/58
- H01L27/088
- H01L27/02
- H01L23/66
- H01L29/417
- H01L21/66
- H10B80/00
- H01L21/822
- H01L29/08
- H01L27/146
- H01L21/033
- H01L21/285
- H01L29/45
- H01L27/12
- H01L23/485
- H01Q9/04
- H01L23/13
- H01Q1/38
- H01Q1/50
- H03K3/037
- G01R31/317
- G01R31/3177
- G11C11/412
- H10B10/00
- H01L27/108
- H10B51/20
- H10B51/10
- H01L27/1159
- H10B53/00
- H10B53/30
- H01L27/16
- H01L35/34
- H01L45/00
- H01L27/24
