Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on April 25th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on April 25th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 46 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (11), H01L23/00 (11), H01L21/02 (9), H01L21/768 (9), H01L23/522 (7)
With keywords such as: layer, semiconductor, structure, region, dielectric, conductive, die, substrate, disposed, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
20240133841.BioFET SYSTEM_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N27/414, H03K19/185
Abstract: a bio-field effect transistor (biofet) system includes a biofet configured to receive to a first voltage signal and output a current signal, where the current signal varies exponentially with respect to the first voltage signal. a logarithmic current-to-time converter is connected to the biofet and is configured to receive the current signal and convert the current signal to a time domain signal. the time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.
Inventor(s): Hao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mill-Jer Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/27, G01R1/04
Abstract: a testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. the circuit board structure includes two edge regions and a main region located therebetween. the first connectors are located over the edge regions and connected to the circuit board structure. the first connecting structure is located over and distant from the circuit board structure. the second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. the first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
Inventor(s): Sandeep Kumar GOEL of Dublin CA (US) for taiwan semiconductor manufacturing company, ltd., Yun-Han LEE of Boashan Township (TW) for taiwan semiconductor manufacturing company, ltd., Saman M.I. ADHAM of Kanata, (CA) for taiwan semiconductor manufacturing company, ltd., Marat GERSHOIG of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/3177, G01R31/28, G01R31/317, G01R31/3185
Abstract: in one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. each set of corresponding latches are operatively connected. a scan path comprises a closed loop comprising each of said first and second plurality of latches. one of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
Inventor(s): Yun-Yue LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
Abstract: a reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. the absorber layer includes one or more layers of an jr based material, a pt based material or a ru based material.
20240134268.LITHOGRAPHY MASK_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chien-Cheng Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Ling Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng Lien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jen Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/32
Abstract: a mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. the light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. in some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.
Inventor(s): Chieh-Hsin HSIEH of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/039, H01L21/027, H01L21/308, H01L29/66
Abstract: a photoresist includes a solvent, a polymer and an additive. the polymer is dissolved in the solvent, and the additive is dispersed in the solvent. the additive includes a double bond or includes an epoxy group. the additive has a surface tension different from a surface tension of the polymer.
Inventor(s): Yueh-Lin Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hung Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
Abstract: a semiconductor processing method includes: selecting a target state of a reticle based on a given data set, wherein the given data set comprises temperature profiles of the reticle correlated to a target overlay performance, and the target state is a state in which a deformation of the reticle is substantially unchanged; regulating the reticle to reach the target state; and performing an exposure process on a target workpiece by using the reticle.
Inventor(s): Chao-Chun Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Boh-Yi Huang of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Chih-yuan Stephen Yu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Yi-Lin Chuang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Sheng Hou of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/337, G06F30/31, G06F30/327, G06F30/3308, G06F30/392
Abstract: systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. a register transfer level code description of logic behavior of a circuit. the register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. a floor plan of each structurally defined circuit design is generated. a physically simulated circuit is created for each floor plan. a range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.
Inventor(s): Sanjeev Kumar Jain of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4074, G11C5/02, G11C5/06, G11C11/4094, G11C11/4096
Abstract: circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. in one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. the boost circuit also includes a transistor and a capacitor. the transistor is coupled to an output of the first inverter. the transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. the capacitor is coupled to an output of the second inverter. the capacitor is configured to generate and provide a delta voltage to the write driver.
Inventor(s): Hung-Chang Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/50, G11C16/08, G11C16/24, G11C16/28, G11C16/30, G11C29/44
Abstract: a memory device includes a memory array, a reference voltage generator and a driver circuit. the memory array includes a memory cell. the reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. the driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.
Inventor(s): Ming-Tung Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-He Chou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B23K26/03, B23K26/53, H01L21/268, H01L21/304, H01L21/66, H01L23/544
Abstract: in some embodiments, the present disclosure relates to an integrated chip fabrication device. the device includes a stealth laser apparatus arranged over a chuck configured to hold a substrate. an infrared camera is arranged over the chuck and configured to detect an alignment mark below the substrate. the alignment mark is used to align the stealth laser apparatus over the chuck. control circuitry is configured to operate the stealth laser apparatus to form a stealth damage region at a location within the substrate that is determined based upon the alignment mark. the stealth damage region separates an inner region of the substrate from an outer region of the substrate.
Inventor(s): Yu-Shih Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Jie Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ying Lee of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Po-Nan Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., U-Ting Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Neng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Bin Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/308, H01L21/8234, H01L29/66, H01L29/78
Abstract: a photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. the photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. the bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
Inventor(s): Ching-Yu Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jei Ming Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/311, H01L21/768
Abstract: a method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. the mask layer is patterned using the patterned photoresist layer as a mask. a target layer is patterned using the patterned mask layer a
Inventor(s): Min-Hsiu Hung of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chien Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsiang Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/285, H01L21/02, H01L21/768, H01L29/66, H01L29/78
Abstract: a method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (pecvd) process; and filling the openings with an electrically conductive material.
Inventor(s): Yung-Chi LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsang-Jiuh WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih CHIOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/027, H01L21/033, H01L21/67
Abstract: a semiconductor device and a semiconductor manufacturing method thereof are provided. the semiconductor manufacturing method includes the following streps. a first semiconductor element with a first bonding film is formed. the first bonding film is formed on a first side of the first semiconductor element. the first semiconductor element and the first bonding film form a taper structure. the first bonding film forms a wide portion of the taper structure. the first semiconductor element forms a narrow portion of the taper structure. a second semiconductor element with a second bonding film is formed. the second bonding film is formed on the second semiconductor element. the first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film. an oxide layer is filled to surround the first semiconductor element and the first bonding film.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, G02B6/122, G02B6/136, G02B6/30, H01L23/00, H01L23/31, H01L23/522, H01L23/528, H01L23/538
Abstract: a method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. the method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. the redistribution lines electrically connect the electronic die to the photonic die. an optical coupler is attached to the photonic die. an optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
Inventor(s): Chun-Jung HUANG of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Lin HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang Huan HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jeff CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Steven HUANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Lun YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, H01L21/67
Abstract: in an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.
Inventor(s): Szu-Ying Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Hong Syue of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/8234, H01L27/088, H01L29/06
Abstract: a method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.
Inventor(s): Shao-Kuan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532, H01L23/535
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip may comprise a first metal line disposed over a substrate. a via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. a first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. a first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
Inventor(s): Tzung-Yi TSAI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Lin LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming CHEN of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/308, H01L21/762, H01L21/8238, H01L27/092, H01L29/06, H01L29/165, H01L29/66, H01L29/78
Abstract: different isolation liners for different type finfets and associated isolation feature fabrication are disclosed herein. an exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. an oxide liner is formed over the first fins in the first region and the second fins in the second region. a nitride liner is formed over the oxide liner in the first region and the second region. after removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. the isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).
Inventor(s): Li-Wei CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Chi SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kai CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yip LOH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Hsu CHEN of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/3205
Abstract: an ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. the protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. the oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. the protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
Inventor(s): Ching-Yi Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsuan Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yip Loh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Hsu Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
Abstract: a method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
Inventor(s): Yu-Chang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Feng Nieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
Abstract: a nanofet transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanofet transistor. the channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. the implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
Inventor(s): Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H01L25/065
Abstract: a semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. the first heat spreader is aside the package structure. the second heat spreader is in physical contact with the first heat spreader. the second heat spreader covers a top surface and sidewalls of the package structure. a material of the first heat spreader is different from a material of the second heat spreader.
Inventor(s): Chung-Jung Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hang Tung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Hsiao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/46, H01L21/52, H01L23/00, H01L23/31, H01L23/40, H01L23/42, H01L23/473, H01L23/498
Abstract: a semiconductor device includes a package and a cooling cover. the package includes a first die having an active surface and a rear surface opposite to the active surface. the rear surface has a cooling region and a peripheral region enclosing the cooling region. the first die includes micro-trenches located in the cooling region of the rear surface. the cooling cover is stacked on the first die. the cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
Inventor(s): Chao-Wen Shih of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ping Pu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Kuei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/525, H01L21/56, H01L23/00, H01L23/29, H01L23/31, H01L23/522, H01L23/532, H01L23/552
Abstract: a method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
Inventor(s): Hsiang-Ku SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Nan LIN of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Man-Yun WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tzu CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Sean YANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hao CHANG of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ling CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/02, H01L21/311, H01L21/3213, H01L21/768, H01L23/00, H01L23/522
Abstract: semiconductor devices and methods of forming the same are provided. in some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. in some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. the method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. the method further includes depositing a nitride layer over the first dielectric layer. in some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/498, H01L25/10
Abstract: provided are a package structure having a joint structure and a method of forming the same. the package structure includes: a first under bump metallurgy (ubm) structure disposed on a first dielectric layer, wherein the first ubm structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first ubm structure and contacting the upper metal layer.
Inventor(s): Wei-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chih Chuang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lin Ho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31
Abstract: a package includes an interposer structure free of any active devices. the interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. the package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. the interconnect device electrically connects the first device die to the second device die.
Inventor(s): Chiang-Jui Chu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Chun Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Young-Hwa Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tao-Sheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065
Abstract: a semiconductor package includes a conductive pillar and a solder. the conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. the solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.
Inventor(s): Wei-Hung Lin of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: according to an exemplary embodiment, a substrate having a first area and a second area is provided. the substrate includes a plurality of pads. each of the pads has a pad size. the pad size in the first area is larger than the pad size in the second area.
Inventor(s): Wen-Chih CHIOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: a semiconductor manufacturing method is provided. the semiconductor manufacturing method includes the following steps. a first semiconductor element with a bonding film and a first stressing film is formed. the first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. the first stressing film makes the first bonding film to have a first convex surface. a second semiconductor element with a second bonding film is formed. the second bonding film is formed on one side of the second semiconductor element. the first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.
Inventor(s): Chien Hung LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Ching ONG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien Jung CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuen-Yi CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Harry-HakLay CHUANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jen WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L23/00, H01L23/48, H01L23/522
Abstract: a semiconductor die package includes an inductor-capacitor (lc) semiconductor die that is directly bonded with a logic semiconductor die. the lc semiconductor die includes inductors and capacitors that are integrated into a single die. the inductors and capacitors of the lc semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. the integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
Inventor(s): Yu-Chien Ku of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Jen Tung of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Ying Liao of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hung Chen of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Fang Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L23/00
Abstract: a semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. the conductive line and the conductive via are disposed in the single-layered dielectric layer. the conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.
Inventor(s): Jhih-Bin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chyi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/08, H01L29/78
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. a plurality of separate isolation structures are disposed within the substrate. the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. a gate electrode is disposed within the substrate. the gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.
Inventor(s): Yin-Kai Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Jiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Lin Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chun Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Ming Hung of Dacun Township (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L29/167, H01L29/49, H01L29/66
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a substrate having a first semiconductor material. a second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. a first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. a silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
Inventor(s): Shih-Cheng CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsiung LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/762, H01L21/764, H01L21/768, H01L21/8238, H01L23/522, H01L29/40
Abstract: a device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. the gate structure is across the active region. the source/drain epitaxial structure is over the active region and adjacent the gate structure. the epitaxial layer is over the source/drain epitaxial structure. the metal alloy layer is over the epitaxial layer. the contact is over the metal alloy layer. the contact etch stop layer lines sidewalls of the source/drain epitaxial structure. the metal alloy layer is spaced apart from the contact etch stop layer.
Inventor(s): Man-Nung SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Hsuan LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/06, H01L29/423, H01L29/49, H01L29/775
Abstract: a semiconductor structure includes a channel structure, a gate structure, two source/drain features, and a plurality of inner spacers. the channel structure includes a plurality of channel features which are spaced apart from each other. the gate structure is disposed to surround the channel features. the source/drain features are disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. each of the inner spacers is disposed to separate the gate structure from a corresponding one of the source/drain features. each of the inner spacers includes an inner spacer body and a lateral nitrided portion. the lateral nitrided portion is in direct contact with the corresponding one of the source/drain features and has a nitrogen content greater than that of the inner spacer body.
Inventor(s): Wen-Kai Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L21/8238, H01L27/088, H01L29/423, H01L29/786
Abstract: improved inner spacers for semiconductor devices and methods of forming the same are disclosed. in an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.
Inventor(s): Yu-Yun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Ting Yen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ting Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd., Tsu-Hsiu Perng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L29/66
Abstract: semiconductor devices and methods of forming the same are provided. a semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. in the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
Inventor(s): Ken-Ichi Goto of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L27/12, H01L29/04, H01L29/49, H01L29/66
Abstract: a semiconductor device includes a substrate, and a first transistor disposed on the substrate. the first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. a crystal orientation of the first channel layer is <100> or <110>. the magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. the first gate electrode is located over the first channel layer. the first gate dielectric is located in between the first channel layer and the first gate electrode. the first source/drain electrodes are disposed on the first channel layer.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L23/522, H01L23/528, H01L27/02
Abstract: a memory device including a rectangular shaped via for at least one vss node connection. in some embodiments, the rectangular shaped via has a length/width of greater than 1.5. the rectangular shaped via may be disposed on the via0 and/or via1 layer interfacing a first metal layer (e.g., m1). the memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. the circular/square shaped vias may be coplanar with the rectangular shaped vias.
Inventor(s): Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L21/3213, H01L21/768, H01L23/522, H10B51/30
Abstract: in accordance with embodiments, a memory array is formed with a multiple patterning process. in embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. after the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. the first conductive material and the second conductive material are etched.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30
Abstract: a ferroelectric memory device and a memory array are provided. the ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. the source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. the channel layer has a bottom planar portion and wall portions. the bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. the work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. the ferroelectric layer separates the channel layer from the work function layer.
Inventor(s): Han-Jong CHIA of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00
Abstract: semiconductor devices are provided. first and second dies are vertically stacked. the first die includes a plurality of memory cells and a plurality of first and second connection features. the memory cells are arranged in rows and columns of a memory array. the first connection features are electrically connected to a plurality of word lines of the memory array. the second connection features are electrically connected to a plurality of bit lines of the memory array. each third connection feature of the second die is electrically connected to a respective first connection feature. each word line driver of the second die is electrically connected to a respective third connection feature. each fourth connection feature of the second die is electrically connected to a respective second connection feature of the first die. each sense amplifier of the second die is electrically connected to a respective fourth connection feature.
Inventor(s): Fa-Shen Jiang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Lien Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bi-Shen Lee of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. a data storage structure overlies the first conductive structure. the data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. the first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. a second conductive structure overlies the data storage structure.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on April 25th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G01N27/414
- H03K19/185
- Taiwan semiconductor manufacturing company, ltd.
- G01R31/27
- G01R1/04
- G01R31/3177
- G01R31/28
- G01R31/317
- G01R31/3185
- G03F1/24
- G03F1/32
- G03F7/039
- H01L21/027
- H01L21/308
- H01L29/66
- G03F7/00
- G06F30/337
- G06F30/31
- G06F30/327
- G06F30/3308
- G06F30/392
- G11C11/4074
- G11C5/02
- G11C5/06
- G11C11/4094
- G11C11/4096
- G11C29/50
- G11C16/08
- G11C16/24
- G11C16/28
- G11C16/30
- G11C29/44
- H01L21/02
- B23K26/03
- B23K26/53
- H01L21/268
- H01L21/304
- H01L21/66
- H01L23/544
- H01L21/8234
- H01L29/78
- H01L21/033
- H01L21/311
- H01L21/768
- H01L21/285
- H01L21/67
- H01L21/56
- G02B6/122
- G02B6/136
- G02B6/30
- H01L23/00
- H01L23/31
- H01L23/522
- H01L23/528
- H01L23/538
- H01L21/677
- H01L21/762
- H01L27/088
- H01L29/06
- H01L23/532
- H01L23/535
- H01L21/8238
- H01L27/092
- H01L29/165
- H01L21/3205
- H01L29/423
- H01L29/775
- H01L29/786
- H01L23/367
- H01L25/065
- H01L23/46
- H01L21/52
- H01L23/40
- H01L23/42
- H01L23/473
- H01L23/498
- H01L23/525
- H01L23/29
- H01L23/552
- H01L21/3213
- H01L21/48
- H01L25/10
- H01L21/683
- H01L25/00
- H01L25/18
- H01L23/48
- H01L27/146
- H01L29/08
- H01L29/10
- H01L29/167
- H01L29/49
- H01L29/417
- H01L21/764
- H01L29/40
- H01L27/12
- H01L29/04
- H10B10/00
- H01L27/02
- H10B51/20
- H10B51/30
- H10B80/00
- H10N70/00
- H10B63/00
- H10N70/20
