Category:Tahir Ghani of Portland OR US
Tahir Ghani
Tahir Ghani from Portland OR US has applied for patents in technology areas such as G11C5/06, G11C11/4091, G11C11/419 with intel corporation.
Patents
Pages in category "Tahir Ghani of Portland OR US"
The following 30 pages are in this category, out of 30 total.
1
- 18467947. CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER (Intel Corporation)
- 18471382. STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE (Intel Corporation)
- 18471402. STACKED MEMORY LAYERS WITH UNIFORM ACCESS (Intel Corporation)
- 18473421. MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION (Intel Corporation)
- 18972346. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING REMOVED SUBSTRATE (Intel Corporation)
- 18978616. FINS FOR METAL OXIDE SEMICONDUCTOR DEVICE STRUCTURES (INTEL CORPORATION)
- 18980999. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING (INTEL CORPORATION)
- 18986226. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS (Intel Corporation)
- 18999778. SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES (Intel Corporation)
- 19000039. INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES (Intel Corporation)
- 19004029. FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM (Intel Corporation)
- 19016771. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES (Intel Corporation)
I
- Intel corporation (20250006547). INTEGRATED CIRCUIT STRUCTURES WITH REMOVED SUB-FIN
- Intel corporation (20250006790). TRANSISTORS WITH ANTIMONY AND PHOSPHORUS DOPED EPITAXIAL SOURCE/DRAIN LAYERS
- Intel corporation (20250006806). HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED LAYER
- Intel corporation (20250008723). THREE-DIMENSIONAL FLOATING BODY MEMORY
- Intel corporation (20250022939). CONTACT OVER ACTIVE GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
- Intel corporation (20250095693). CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
- Intel corporation (20250104760). STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Intel corporation (20250107107). STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Intel corporation (20250107108). MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Intel corporation (20250107181). GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING REMOVED SUBSTRATE
- Intel corporation (20250113550). GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING
- Intel corporation (20250113607). FINS FOR METAL OXIDE SEMICONDUCTOR DEVICE STRUCTURES
- Intel corporation (20250120152). GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS
- Intel corporation (20250126832). SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
- Intel corporation (20250133821). INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES
- Intel corporation (20250142870). FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Intel corporation (20250151338). GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES
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