Category:Debendra Mallik of Chandler AZ (US)
Debendra Mallik of Chandler AZ (US)
Executive Summary
Debendra Mallik of Chandler AZ (US) is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (6 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), and they have worked with companies such as Intel Corporation (7 patents). Their most frequent collaborators include (5 collaborations), (4 collaborations), (4 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
- H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
- H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
- H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents
- H01L2224/08137 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
- H01L21/486 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
- H01L23/3738 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L23/49894 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
- H01L2224/08245 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/15311 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/473 (by flowing liquids {(): 1 patents
- H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L24/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/08165 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/24051 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/24137 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/01029 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/1435 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
- H01L23/564 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/05541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/05647 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/80357 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/80379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/04642 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/0504 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/059 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
- H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 1 patents
- H01L2224/08121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/08225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/1205 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/17 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/16 (Fillings or auxiliary members in containers {or encapsulations}, e.g. centering rings (): 1 patents
- H01L23/3675 (Cooling facilitated by shape of device {(): 1 patents
- H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/17051 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/1713 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/17163 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/17181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/17519 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
Companies
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List of Companies
- Intel Corporation: 7 patents
Collaborators
- Nitin A. Deshpande of Chandler AZ (US) (5 collaborations)
- Sagar Suthram of Portland OR (US) (4 collaborations)
- Wilfred Gomes of Portland OR (US) (4 collaborations)
- Pushkar Sharad Ranade of San Jose CA (US) (4 collaborations)
- Ravindranath Vithal Mahajan of Chandler AZ (US) (4 collaborations)
- Abhishek A. Sharma of Portland OR (US) (4 collaborations)
- Ram Viswanath of Phoenix AZ (US) (1 collaborations)
- Xavier Brun of Hillsboro OR (US) (1 collaborations)
- Omkar G. Karhade of Chandler AZ (US) (1 collaborations)
- Mohammad Enamul Kabir of Portland OR (US) (1 collaborations)
- Joshua Fryman of Corvallis OR (US) (1 collaborations)
- Stephen Morein of San Jose CA (US) (1 collaborations)
- Matthew Adiletta of Bolton MA (US) (1 collaborations)
- Michael Crocker of Portland OR (US) (1 collaborations)
- Aaron Gorius of Upton MA (US) (1 collaborations)
- Sergio Antonio Chan Arguedas of Chandler AZ (US) (1 collaborations)
- Jimin Yao of Chandler AZ (US) (1 collaborations)
- Chandra Mohan Jha of Tempe AZ (US) (1 collaborations)
Subcategories
This category has the following 6 subcategories, out of 6 total.
A
D
N
O
S
W
Pages in category "Debendra Mallik of Chandler AZ (US)"
The following 38 pages are in this category, out of 38 total.
1
- 17846086. PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)
- 17846109. PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING simplified abstract (Intel Corporation)
- 17846129. PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)
- 17846153. PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)
- 17846173. PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)
- 17957403. HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRATED CIRCUIT DEVICES simplified abstract (Intel Corporation)
- 17957926. INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME simplified abstract (Intel Corporation)
- 18148528. PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract (Intel Corporation)
- 18148533. PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract (Intel Corporation)
- 18148543. PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract (Intel Corporation)
- 18217049. METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES (Intel Corporation)
- 18367285. INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES simplified abstract (Intel Corporation)
- 18395351. IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS simplified abstract (Intel Corporation)
- 18397906. NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION simplified abstract (Intel Corporation)
- 18397915. HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS simplified abstract (Intel Corporation)
- 18400784. STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE simplified abstract (Intel Corporation)
- 18462600. MICROELECTRONIC STRUCTURES INCLUDING BRIDGES simplified abstract (Intel Corporation)
- 18611534. GLASS CORE PATCH WITH IN SITU FABRICATED FAN-OUT LAYER TO ENABLE DIE TILING APPLICATIONS simplified abstract (Intel Corporation)
- 18818285. LOCALIZED HIGH DENSITY SUBSTRATE ROUTING (Intel Corporation)
- 18955613. IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER (Intel Corporation)
I
- Intel corporation (20240113087). HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRATED CIRCUIT DEVICES simplified abstract
- Intel corporation (20240113088). INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME simplified abstract
- Intel corporation (20240128162). NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION simplified abstract
- Intel corporation (20240128205). HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS simplified abstract
- Intel corporation (20240136244). IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS simplified abstract
- Intel corporation (20240136278). STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE simplified abstract
- Intel corporation (20240222321). PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract
- Intel corporation (20240222326). PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract
- Intel corporation (20240222328). PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REGIONS simplified abstract
- Intel corporation (20240234225). GLASS CORE PATCH WITH IN SITU FABRICATED FAN-OUT LAYER TO ENABLE DIE TILING APPLICATIONS simplified abstract
- Intel corporation (20240421073). LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Intel corporation (20250062278). PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER INTERCONNECTS
- Intel corporation (20250079263). PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING MICROCHANNEL
- Intel corporation (20250079392). HYBRID BONDING INTERCONNECT (HBI) ARCHITECTURES AND METHODS FOR SCALABILITY
- Intel corporation (20250079398). PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE REGULATORS
- Intel corporation (20250079399). PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STATE BATTERY
- Intel corporation (20250087548). IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER
Categories:
- Nitin A. Deshpande of Chandler AZ (US)
- Sagar Suthram of Portland OR (US)
- Wilfred Gomes of Portland OR (US)
- Pushkar Sharad Ranade of San Jose CA (US)
- Ravindranath Vithal Mahajan of Chandler AZ (US)
- Abhishek A. Sharma of Portland OR (US)
- Ram Viswanath of Phoenix AZ (US)
- Xavier Brun of Hillsboro OR (US)
- Omkar G. Karhade of Chandler AZ (US)
- Mohammad Enamul Kabir of Portland OR (US)
- Joshua Fryman of Corvallis OR (US)
- Stephen Morein of San Jose CA (US)
- Matthew Adiletta of Bolton MA (US)
- Michael Crocker of Portland OR (US)
- Aaron Gorius of Upton MA (US)
- Sergio Antonio Chan Arguedas of Chandler AZ (US)
- Jimin Yao of Chandler AZ (US)
- Chandra Mohan Jha of Tempe AZ (US)
- Debendra Mallik of Chandler AZ (US)
- Inventors
- Inventors filing patents with Intel Corporation