18478391. ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS (INTEL CORPORATION)
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS
Organization Name
Inventor(s)
Andrey Vyatskikh of Hillsboro OR US
Adel Elsherbini of Chandler AZ US
Brandon M. Rawlings of Chandler AZ US
Tushar Kanti Talukdar of Wilsonville OR US
Thomas L. Sounart of Chandler AZ US
Johanna Swan of Scottsdale AZ US
Grant M. Kloster of Lake Oswego OR US
Carlos Bedoya Arroyave of Portland OR US
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS
This abstract first appeared for US patent application 18478391 titled 'ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS
Original Abstract Submitted
An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.
Categories:
- INTEL CORPORATION
- Feras Eid of Chandler AZ US
- Andrey Vyatskikh of Hillsboro OR US
- Adel Elsherbini of Chandler AZ US
- Brandon M. Rawlings of Chandler AZ US
- Tushar Kanti Talukdar of Wilsonville OR US
- Thomas L. Sounart of Chandler AZ US
- Kimin Jun of Portland OR US
- Johanna Swan of Scottsdale AZ US
- Grant M. Kloster of Lake Oswego OR US
- Carlos Bedoya Arroyave of Portland OR US
- H01L21/683
- H01L23/00
- H01L23/538
- CPC H01L21/6835