International Business Machines Corporation patent applications published on November 30th, 2023

Summary of the patent applications from International Business Machines Corporation on November 30th, 2023

Recently, International Business Machines Corporation (IBM) has filed several patents related to various technologies. These patents cover a range of areas including memory devices, electromagnetic compatibility (EMC) protection apparatus, device identification, access policy optimization, semiconductor devices, CMOS devices, microelectronic structures, contact and gate regions, and language learning through content translation.

In the field of memory devices, IBM has filed a patent for a memory device that includes a magnetic tunnel junction pillar and a sidewall spacer. This design aims to improve the performance and functionality of the memory device.

For EMC protection apparatus, IBM has filed a patent for a system and method to control the apparatus in a removable component inserted into an end product. The system detects a power good signal and rotates the EMC protection device to create an EMC seal.

In the area of device identification, IBM has filed a patent for a method to display identification information for devices connected to multiple ports. The method involves establishing communication between the device and the port and displaying the identification information on a display associated with the port.

IBM has also filed a patent for a system and method to analyze and optimize access policies. The system computes an access control health metric to measure the current state of access policies and identifies subgroups of policies for optimization.

In the field of semiconductor devices, IBM has filed a patent for a device design that includes a buried power rail, buried oxide layer, channel fins, bottom epitaxial layer, gate stack, and top epitaxial layer. This design aims to improve electrical connectivity and performance.

IBM has also filed a patent for a CMOS device with a pFET epi and an nFET epi, each having specific dielectric layers and trench structures.

In the area of microelectronic structures, IBM has filed a patent for a structure with stacked device regions, gate cut regions, and interconnects connecting different devices within the stacked region.

IBM has also filed a patent for a microelectronics device with a specific design for the contact and gate regions, including tapered sidewalls.

Lastly, IBM has filed a patent for a magnetic tape head, magnetic tape drive, and computational device, although further details are not provided in the abstract.

Notable applications:

• Memory device with magnetic tunnel junction pillar and sidewall spacer.
• System and method for controlling EMC protection apparatus in a removable component.
• Method for displaying identification information for devices connected to multiple ports.
• System and method for analyzing and optimizing access policies.
• Semiconductor device with buried power rail, buried oxide layer, and gate stack.
• CMOS device with specific dielectric layers and trench structures.
• Microelectronic structure with stacked device regions and interconnects.
• Microelectronics device with specific design for contact and gate regions.
• Magnetic tape head, magnetic tape drive, and computational device.

Patent applications for International Business Machines Corporation on November 30th, 2023

FILTER DEVICE HAVING MULTIPLE CHANGEABLE FILTER SURFACES (17664925)

Main Inventor

Madhana Sunder

Brief explanation

The patent application describes a device that consists of an outer component, an inner component, and a filter module.

• The outer component is a hollow cylinder with ports on its sidewalls.
• The inner component is positioned inside the outer component and also has a cylinder shape with ports aligned parallel to the exterior ports.
• The filter module is a hollow prism surrounding the inner component and has four faces that can hold filters.
• The filter module also has vanes along the edges that form seals with the outer component.
• One of the faces of the filter module has a filter that is aligned between a pair of interior and exterior ports.

Abstract

A device that comprises an outer component, an inner component and a filter module. The outer component includes a first hollow cylinder, and exterior ports in sidewalls of the first hollow cylinder. The inner component is positioned coaxially within the first hollow cylinder, and includes a second cylinder, and interior ports in the second cylinder, wherein the interior fluid ports are aligned parallel to the exterior ports. The filter module includes a hollow prism positioned coaxially within the outer component and surrounding the inner component, the hollow prism comprising at least four faces configured to retain filters. The filter module also includes vanes positioned along edges connecting the at least four faces and forming seals with the first hollow cylinder. A first filter is provided on a first face, of the at least four faces, which is aligned between a pair of the interior and exterior ports.

VISUAL LIGHT-BASED DIRECTION TO ROBOTIC SYSTEM (17664734)

Main Inventor

Shailendra Moyal

Brief explanation

The patent application describes a method, computer system, and computer program for light-based navigation of a robotic device.

• The method involves detecting a light beam and identifying its source and endpoint locations.
• A voice command is received to proceed to the endpoint location.
• The robotic device is instructed to directly move to the endpoint location.
• Once the robotic device reaches the endpoint location, it is instructed to perform an activity there.

Abstract

According to one embodiment, a method, computer system, and computer program product for light-based navigation of robotic device. The embodiment may include detecting a light beam. The embodiment may include identifying a source location and an endpoint location of the light beam. The endpoint location comprises a location where the light beam intersects a surface. The embodiment may include receiving a voice command to proceed to the endpoint location. The embodiment may include instructing a mobile robotic device to proceed directly to the endpoint location. In response to the mobile robotic device reaching the endpoint location, the embodiment may include instructing the mobile robotic device to perform an activity therein.

PATH DISCOVERY IN AN UNKNOWN ENCLOSED SURROUNDING BASED ON DIRECTION OF LIGHT AND AIR MOVEMENT (17804101)

Main Inventor

Atul Mene

Brief explanation

The patent application describes a technology that helps a robot navigate and find an exit in an environment. Here are the key points:

• The technology includes a processor that keeps track of the robot's location in the environment.
• The processor uses environment sensors to capture information about the surroundings.
• By analyzing the captured data, the processor determines the best location for the robot to exit the environment.
• To ensure the chosen exit route is safe and reliable, the processor validates it using historical data.
• Finally, the processor communicates the validated exit route to the robot, allowing it to navigate and reach the exit successfully.

Abstract

The present invention may include a processor that monitors location of a robot in an environment. The processor captures the environment with one or more environment sensors. The processor analyzes the captured environment to determine an exit location. The processor validates an exit route based on historical data and the exit location and communicates the exit route to the robot.

RANKING A USER'S PREFERENCE MODEL IN A VIRTUAL REALITY ENVIRONMENT (17804604)

Main Inventor

Jill Burns

Brief explanation

- This patent application describes a method, computer system, and computer program for mapping user preferences in augmented reality/virtual reality (AR/VR) environments.

- The method involves capturing user preferences through user feedback while they interact with elements in the AR/VR space. - The captured user preferences are then mapped to clusters, which group similar preferences together. - Based on the mapped user preferences, a user preference model of the elements in the AR/VR space is generated. - The user preference model is then displayed within the AR/VR space, allowing users to see and interact with elements that align with their preferences. - The innovation aims to enhance the user experience in AR/VR environments by personalizing the elements based on individual preferences.

Abstract

According to one embodiment, a method, computer system, and computer program product for augmented reality/virtual reality (AR/VR) preference mapping is provided. The embodiment may include capturing a plurality of user preferences from a plurality of user feedback while a user interacts with elements of an AR/VR space. The embodiment may also include mapping one or more user preferences from the plurality of captured user preferences to one or more clusters. The embodiment may further include generating a user preference model of the elements based on the one or more mapped user preferences. The embodiment may also include displaying the user preference model in the AR/VR space.

ZOOM ACTION BASED IMAGE PRESENTATION (17664710)

Main Inventor

Tushar Agrawal

Brief explanation

The patent application is about a zoom action based image presentation system.

• The system receives a zoom action on a first image from a user device.
• The zoom action has specific parameters that define how the zoom should be performed.
• The system analyzes the first image to determine its properties.
• Based on the zoom action parameters and the properties of the first image, the system searches for a second image that depicts a different structural level of the first image.
• The second image is then presented to the user as a response to the zoom action.

Abstract

Aspects of the present disclosure relate to zoom action based image presentation. A zoom action on a first image can be received on a user device, the zoom action defined by a set of zoom action parameters. The first image can be analyzed to determine image properties of the first image. A second image depicting a different structural level of the first image can be searched for based on the zoom action parameters of the zoom action and the image properties of the first image. The second image can be presented to the user as a response to the received zoom action.

INFERRING THE STATE OF A WRITE-ONLY DEVICE (18363102)

Main Inventor

Jarrett Betke

Brief explanation

The patent application describes techniques for inferring the state of a write-only device.

• The system includes a processor that executes computer executable components stored in memory.
• The computer executable components consist of a monitor component and a state component.
• The monitor component compares a property of a feedback signal from the write-only device with a reference signal.
• The state component determines the state of the write-only device based on the comparison between the property and the reference signal.

Abstract

Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.

BINARY TRANSLATION USING RAW BINARY CODE WITH COMPILER PRODUCED METADATA (17664969)

Main Inventor

Toshihiko Koju

Brief explanation

The abstract describes a method, system, and computer-readable medium for binary translation.

• The binary translator combines raw binary code with compiler-produced metadata.
• The translator uses the metadata to reconcile control flow information and aliasing information in the raw binary code.
• It prevents copy propagation of values in temporary variables beyond certain offsets in the machine instructions.
• It removes dead store instructions.
• It generates an optimized version of a compiled program module that is compatible with the original version.

Abstract

A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed. The binary translator further caused to remove identified dead store instructions, and to generate a new compiled program module comprising an optimized version of the compiled program module having strict compatibility to an original version of the compiled program module.

COMPATIBLE AND SECURE SOFTWARE UPGRADES (17804322)

Main Inventor

Jun Wang

Brief explanation

- The patent application describes techniques for managing machine learning libraries in a machine learning platform.

- The techniques involve creating a table that lists the machine learning libraries used in a deployed machine learning platform instance, along with their current versions. - The table also includes information about available version upgrades for each library, including a security indication and a compatibility indication. - Based on this information, the techniques generate recommendations for upgrading the machine learning libraries. - The recommendations take into account both the security indication, which indicates the level of security provided by the available version upgrade, and the compatibility indication, which indicates how well the available version upgrade will work with the current version of the library. - The goal of these techniques is to simplify the process of managing machine learning libraries and ensure that the platform is using the most secure and compatible versions.

Abstract

Described are techniques for machine learning library management. The techniques include generating a table including a plurality of machine learning libraries and their current versions that are used in a deployed machine learning platform (MLP) instance, a first available version upgrade for a first machine learning library of the plurality of machine learning libraries, a security indication associated with the first available version upgrade relative to a current version implemented by the first machine learning library, and a compatibility indication between the first available version upgrade and the current version of the first machine learning library. The techniques further include generating a recommendation related to upgrading the first machine learning library based on the security indication and the compatibility indication.

CACHE MANAGEMENT USING CACHE SCOPE DESIGNATION (17664722)

Main Inventor

Taylor J. Pritchard

Brief explanation

The patent application describes a cache controller that helps improve the processing of cache lines that are being accessed by multiple requestors. Here are the key points:

• The cache controller receives a fetch request for data from a requestor.
• The fetch request includes a cache scope designation, indicating the level of cache where the data may be found.
• If the requested data is already present in the high-level cache associated with the requestor (e.g., L1 cache), the cache controller immediately returns the data to the requestor.
• If the data is not in the high-level cache or if it is not within the cache pool identified by the cache scope designation, the cache controller returns a cache miss, undeliverable data, and request done instruction to the requestor.
• This approach allows the requestor to decide when and if address contention events are necessary or important.
• By allowing address contention events, the system can reduce performance issues, latencies, execution times, and inefficient use of resources.

Abstract

To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

ELECTRONIC COMMUNICATION BETWEEN DEVICES USING A PROTOCOL (17664806)

Main Inventor

Timothy Andrew Moran

Brief explanation

The patent application describes a method for communication between devices using protocol commands.

• The method involves accessing a key that maps different patterns of stimuli and protocol commands to messages.
• A device sends a pattern of stimuli to prompt a corresponding pattern of protocol commands to be sent to other devices of the same type.
• The protocol commands are compliant with the Small Computer System Interface (SCSI) specification.
• A specific pattern of protocol command stimuli can be sent to communicate a mapped message to other devices.

Abstract

Communication between target devices using protocol commands being carried out by a target device includes accessing a key for mapping of a plurality of defined patterns of stimuli and defined patterns of resultant protocol commands to a plurality of messages. A defined pattern of stimuli is sent from a target device to an initiator device to prompt a resultant defined pattern of protocol commands to be sent from the initiator device to all target devices that identify as the same device. The protocol commands including Small Computer System Interface (SCSI) specification compliant commands. A selected pattern of protocol command stimuli is sent from a first target device to the initiator device to prompt a resultant pattern of protocol commands from the initiator device to all target devices that identify as the same device thereby communicating the mapped message to other target devices.

FULL ALLOCATION VOLUME TO DEDUPLICATION VOLUME MIGRATION IN A STORAGE SYSTEM (17804109)

Main Inventor

Dominic Tomkins

Brief explanation

- The patent application describes a method, computer program product, and computer system for migrating data from a full allocation volume to a deduplication volume in a storage system.

- The method involves moving the physical allocation of stored data from the full allocation volume to a virtual address range in a deduplication domain. - The deduplication metadata is set up to be a passthrough, meaning it allows the data to pass through without being processed. - Once the virtual address range is populated with the physical allocations, a background deduplication process is performed. - The deduplication process involves using a drive query hash interface to perform hash calculations on the physical drives where the data is stored. - The purpose of the deduplication process is to identify and eliminate duplicate data, reducing storage space requirements. - The innovation lies in the efficient migration of data from a full allocation volume to a deduplication volume, and the use of a passthrough metadata setup and background deduplication process. - This method and system can be implemented in a computer program product and computer system to improve storage efficiency and reduce storage costs.

Abstract

A method, computer program product, and computer system for full allocation volume to deduplication volume migration in a storage system. The method includes moving a physical allocation of stored data associated with a full allocation volume into a virtual address range in a deduplication domain and setting up the deduplication metadata to be a passthrough. The method then performs a background deduplication process on the virtual address range once populated with the physical allocations using a drive query hash interface to perform hash calculations on physical drives at which the data is stored.

DATA QUALITY ANALYZE EXECUTION IN DATA GOVERNANCE (17824200)

Main Inventor

Xu Bin Cai

Brief explanation

- The patent application describes an approach for retrieving fingerprint configuration sets for a given data source and using these sets to generate corresponding fingerprints.

- These fingerprints are then compared to a repository of stored fingerprints. - If a match is found, the data quality configuration set is retrieved from the repository and used for data quality analysis. - If no match is found, one of the configuration sets is selected for data quality analysis and the repository is updated accordingly. - The approach aims to improve data quality analysis by utilizing fingerprint configuration sets and matching them with stored fingerprints.

Abstract

An approach is provided that retrieves fingerprint configuration sets corresponding to a received data source and uses the configuration sets to generate fingerprints that correspond to the data source. These fingerprints are compared to a number of fingerprints that are stored in a repository. If a match is found, then the data quality configuration set is retrieved from the repository and used to perform a data quality analysis. On the other hand, if a match is not found, then one of the configuration sets is selected to perform the data quality analysis on the received data source and the repository is updated so that the selected fingerprint configuration set corresponds to the received data source.

MANAGING LOCATIONS OF DERIVED STORAGE OBJECTS (17664880)

Main Inventor

Ben Sasson

Brief explanation

- The patent application describes techniques for managing data locations of derived storage objects.

- The techniques involve using a primary metadata tree to locate data for a primary object in physical storage. - The primary metadata tree also provides lookup paths for derived objects, which are views of the primary object at specific points in time. - The sub-tree of the primary metadata tree contains copy leaf nodes that point to stored data of the derived objects. - An ancestry graph is maintained to link derived object identifiers and provide a way to identify the closest stored physical data of a derived object.

Abstract

Described are techniques for managing data locations of derived storage objects. The techniques include accessing a primary metadata tree providing a lookup path using a virtual address to locate data for a primary object in physical storage pointed to by a leaf node of the primary metadata tree and providing a sub-tree from a leaf node of the primary metadata tree associated with the primary object, the sub-tree providing lookup paths using virtual addresses for derived objects. Wherein a derived object is a view of the primary object at a specific point in time, with copy leaf nodes of the sub-tree pointing to stored data of the derived objects. The techniques further include maintaining an ancestry graph associated with the sub-tree with the ancestry graph linking derived object identifiers to provide an ancestral chain lookup to identify derived object identifiers of the closest stored physical data of a derived object.

IDENTIFYING AND PROCESSING POLY-PROCESS NATURAL LANGUAGE QUERIES (17804116)

Main Inventor

YAZAN OBEIDI

Brief explanation

This patent application describes a system for identifying and processing complex natural language queries. Here are the key points:

• The system receives a natural language query.
• It automatically identifies a bridge entity in the query.
• It determines if the query is a poly-process query (involving multiple processes).
• If it is a poly-process query, the system generates sub-queries for each process and generates results for each sub-query.
• The system combines the results of each sub-query using the bridge entity to produce a combined result.
• It then generates a modified sub-query for post-processing of the combined result.
• The modified sub-query is processed to generate a final query result for the original natural language query.

Abstract

An embodiment for identifying and processing poly-process natural language queries may include receiving a natural language query. The embodiment may also automatically identify a bridge entity in the received natural language query. The embodiment may also automatically determine whether the received natural language query is a poly-process query. The embodiment may further include, in response to identifying that the received natural language query is the poly-process query, automatically generating sub-queries for each process in the poly-process query and generate results for each sub-query. The embodiment may also automatically combining the results of each sub-query using the bridge entity to output a combined result. The embodiment may further include automatically generating a modified sub-query for post-processing of the combined result. The embodiment may also automatically process the modified sub-query to generate a final query result for the received natural language query.

LOGIC LOCKING OPERATIONS (17664861)

Main Inventor

Jinwook JUNG

Brief explanation

The patent application describes a method for enhancing the protection of an integrated circuit in a computing system using a processor.

• The method involves applying a logic locking FSM component or a logic locking with RTL gating to the current design logic of the integrated circuit.
• This allows for the activation and protection of the integrated circuit's operations without modifying the current design logic.
• The activation of the integrated circuit is dependent on providing the correct key from the logic locking FSM component or the logic locking with RTL gating.

Abstract

Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.

ENHANCED ALIGNMENT FOR GLOBAL PLACEMENT IN A CIRCUIT (17804070)

Main Inventor

Alexey Y LVOV

Brief explanation

The patent application describes a method for improving the initial placement of components in a circuit design using a computer processor.

• The method uses a wire length minimization technique based on maximum population density constraints.
• It applies single player game theory principles to optimize the global placement of an integrated circuit.
• The goal is to minimize the length of the wires connecting different components in the circuit design.
• By considering population density constraints, the method ensures that components are placed in a way that minimizes interference and maximizes efficiency.
• The method is implemented in a computing system using a processor.

Abstract

Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

DETECTING PEER PRESSURE USING MEDIA CONTENT INTERACTIONS (17804232)

Main Inventor

Yuriko Nishikawa

Brief explanation

The patent application describes a method, computer system, and computer program for detecting peer pressure.

• The invention involves receiving a contentious statement about a topic and identifying related media content.
• Social interactions related to the media content are analyzed, including aggregating the interactions.
• Balance values are calculated based on the aggregations, indicating the level of peer pressure.
• Time-series data is generated and outputted, providing a visual representation of the balance values over time.

Abstract

A method, computer system, and a computer program for detecting peer pressure is provided. The present invention may include receiving at least one input including a contentious statement relating to a topic and detecting a plurality of media content associated with the topic. The present invention may then include determining a plurality of social interactions including at least one aggregation associated with the plurality of media content. The present invention may further include calculating a plurality of balance values associated with the plurality of social interactions based on the at least one aggregation. The present invention may further include outputting a plurality of time-series data associated with the plurality of balance values.

PARALLEL AND DISTRIBUTED PROCESSING OF PROPOSITIONAL LOGICAL NEURAL NETWORKS (17804107)

Main Inventor

Venkatesan Thirumalai Chakaravarthy

Brief explanation

The patent application describes a system that uses a processor to identify weights in a propositional logical neural network and convert them into a sparse matrix. The system also converts a training set into bound vectors and updates the sparse matrix using a graphical processing unit (GPU). It computes a loss parameter and updates the weights of the neural network if the loss function is below a certain threshold.

• System identifies weights in a propositional logical neural network
• Weights are converted into a sparse matrix
• Training set is converted into bound vectors
• Sparse matrix is updated using a graphical processing unit (GPU)
• Loss parameter is computed
• Weights of the neural network are updated if loss function is below a threshold

Abstract

An embodiment may include a processor that identifies a plurality of weights from the propositional logical neural network. The embodiment may convert the plurality of weights into a sparse matrix. The embodiment may convert a training set into a plurality of bound vectors. The embodiment may update the sparse matrix using a graphical processing unit (GPU). The embodiment may compute a loss parameter and based on determining the loss function is below threshold, update the plurality of weights of the propositional neural network.

NEUROMORPHIC CHIP FOR UPDATING PRECISE SYNAPTIC WEIGHT VALUES (18366348)

Main Inventor

Atsuya Okazaki

Brief explanation

The patent application describes a neuromorphic chip design that includes synaptic cells, resistive devices, axon lines, dendrite lines, and switches.

• The chip has a crossbar array formed by connecting the synaptic cells to the axon and dendrite lines.
• The axon lines receive input data and supply it to the synaptic cells.
• The dendrite lines receive output data and supply it through output lines.
• The switches connect input terminals to input lines and can changeably connect output terminals to axon lines.

Abstract

A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

METHOD AND SYSTEM OF GENERATING A CLASSICAL MODEL TO SIMULATE A QUANTUM COMPUTATIONAL MODEL VIA INPUT PERTURBATION TO ENHANCE EXPLAINABILITY (17825614)

Main Inventor

Vladimir Rastunkov

Brief explanation

The patent application describes a method for generating a classical model to simulate a quantum computational model.

• Input dataset into a quantum computational model implemented on a quantum computer.
• Compute output results using the quantum computer.
• Introduce a variation to at least a portion of the dataset into the quantum computer.
• Compute updated output results based on the variation using the quantum computer.
• Generate a classical twin model of the quantum computational model based on the relationship between the output results, updated output results, and the dataset.

Abstract

A method of generating a classical model to simulate a quantum computational model includes 1) inputting into a quantum computational model a dataset, the quantum computational model being implemented on a quantum computer, 2) computing output results with the quantum computational model using the quantum computer, 3) introducing a variation to at least a portion of the dataset into the quantum computer, 4) computing updated output results of the quantum computational model based on the variation of the at least the portion of the dataset using the quantum computer, and 5) generating a classical twin model of the quantum computational model based on a relationship of the output results and updated output results to the dataset from the quantum computational model.

DATA SELECTION FOR MACHINE LEARNING MODELS BASED ON DATA PROFILING (17804218)

Main Inventor

Paulina Toro Isaza

Brief explanation

The patent application describes a method, computer system, and computer program for data selection.

• The invention involves generating a first model for a dataset and determining its performance level based on various dataset metric values.
• If the first model's performance level fails to exceed a performance threshold, the invention creates multiple data subsets from the dataset.
• The invention calculates subset metric values for each data subset and generates a second model based on these values.
• The second model's performance level is then determined, and if it exceeds the performance threshold, an optimization associated with the first model is determined.

Abstract

A method, computer system, and a computer program for data selection is provided. The present invention may include generating a first model associated with a dataset. The present invention may further include determining a first model performance level associated with the first model based on a plurality of dataset metric values of the dataset. The present invention may further include a plurality of data subsets of a dataset based on the first model performance level failing to exceed a performance threshold and calculating a plurality of subset metric values associated with the plurality of data subsets. The present invention may further include generating a second model associated with at least one data subset based on the plurality of subset metric values and determining an optimization associated with the first model based on a second model performance level associated with the second model exceeding the performance threshold.

GRAPH ENCODERS FOR BUSINESS PROCESS ANOMALY DETECTION (17664719)

Main Inventor

Siyu Huo

Brief explanation

The patent application describes a method, computer system, and computer program for detecting anomalies in business process logs.

• Converts business process logs into a graphical data structure.
• Generates an optimized graph encoding for anomaly detection using unsupervised machine learning.
• Computes an anomaly score for each activity in the business process log using a process aware metric based on feature representation.
• Labels data points with high anomaly scores.

Abstract

A method, computer system, and a computer program product for anomaly detection is provided. The present invention may include converting business process logs into a graphical data structure. The present invention may include generating an optimized graph encoding for anomaly detection using an unsupervised machine learning model. The present invention may include computing an anomaly score for each activity of the business process log using a process aware metric based on feature representation. The present invention may include labeling each of the one or more data points with a high anomaly score.

PREDICTIVE SERVICE ORCHESTRATION USING THREAT MODELING ANALYTICS (17664718)

Main Inventor

ASMAHAN ALI

Brief explanation

- This patent application describes a computer-implemented method, system, and computer program product for predictive service orchestration using threat modeling analytics.

- The method involves identifying attributes of a client computing environment and collecting threat modeling content for various vendor computing environments. - The threat modeling content is then analyzed and compared with the attributes of the client computing environment. - Based on this comparison, a client threat model is generated for the client computing environment. - The innovation aims to provide a predictive service orchestration system that can assess potential threats in a client's computing environment by analyzing threat modeling content from different vendors. - This can help in identifying and addressing potential security risks and vulnerabilities in the client's system. - The system utilizes threat modeling analytics to provide a more accurate and comprehensive understanding of the threats that may affect the client's computing environment. - By generating a client threat model, the system can assist in making informed decisions regarding service orchestration and security measures for the client's system.

Abstract

Provided is a computer-implemented method, system, and computer program product for predictive service orchestration using threat modeling analytics. A processor may identify a plurality of attributes of a client computing environment. The processor may collect threat modeling content for a plurality of vendor computing environments. The processor may analyze the threat modeling content for the plurality of vendor computing environments. The processor may compare the analyzed threat modeling content for the plurality of vendor computing environments with the plurality of attributes of the client computing environment. The processor may generate, based on the comparing, a client threat model for the client computing environment.

Lesion Detection and Segmentation (17752506)

Main Inventor

Wen Wei

Brief explanation

The patent application describes mechanisms for detecting lesions in diffusion weighted imaging (DWI) images.

• The mechanisms receive a set of DWI images of an anatomical structure from a medical imaging computer system.
• The set of DWI images includes multiple images with different b-values.
• The mechanisms generate a second set of DWI images by applying a predetermined criterion to the first set of images.
• The second set of DWI images includes images with different b-values.
• The mechanisms extract feature data from the second set of DWI images.
• The feature data is input into one or more computer neural networks.
• The neural networks process the feature data and generate an output.
• The output can include a classification of the lesion or a mask indicating the presence of a lesion.

Abstract

Mechanisms are provided for detecting lesions in diffusion weighted imaging (DWI) images. The mechanisms receive a first set of DWI images corresponding to a anatomical structure, from medical imaging computer system(s). The first set of DWI images comprises a plurality of DWI images having at least two different b-values. The mechanisms generate a second set of DWI images from the first set of DWI images based on at least one predetermined criterion. The second set of DWI images comprises different DWI images having different b-values. The mechanisms extract feature data from the second set of DWI images, input the feature data into at least one computer neural network, and generate an output from the neural network(s) comprising at least one of a lesion classification or a lesion mask based on results of processing, by the neural network(s), of the feature data extracted from the second set of DWI images.

REGIONAL-TO-LOCAL ATTENTION FOR VISION TRANSFORMERS (17804724)

Main Inventor

Richard CHEN

Brief explanation

- The patent application describes techniques and apparatus for analyzing visual content using a visual transformer.

- The visual content item is divided into regions, and a first set of tokens is generated, with each token representing a regional feature from a different region. - A second set of tokens is generated, with each token representing a local feature from one of the regions. - Using a hierarchical vision transformer, at least one feature map is generated by analyzing the first set of tokens and the second set of tokens separately. - Based on the feature map, at least one vision task is performed. - The innovation allows for efficient analysis of visual content by utilizing regional and local features and a hierarchical vision transformer.

Abstract

Techniques and apparatus for analyzing visual content using a visual transformer are described. An example technique includes generating a first set of tokens based on a visual content item. Each token in the first set of tokens is associated with a regional feature from a different region of a plurality of regions of the visual content item. A second set of tokens is generated based on the visual content item. Each token in the second set of tokens is associated with a local feature from one of the plurality of regions of the visual content item. At least one feature map is generated for the visual content item, based on analyzing the first set of tokens and the second set of tokens separately using a hierarchical vision transformer. At least one vision task is performed based on the at least one feature map.

AUTOMATED HAZARD RECOGNITION USING MULTIPARAMETER ANALYSIS OF AERIAL IMAGERY (17825483)

Main Inventor

Levente Klein

Brief explanation

- The patent application describes a method for identifying the type of tree in an image and assessing the risk of it coming into contact with a power line.

- The method involves using edge-detection processing to segment the tree in the image and create a contour line that outlines its perimeter. - The system then compares the contour line to contour lines of different tree species to determine the type of tree. - The diameter of the tree's crown is calculated using the contour line, and this information is used to estimate the tree's height. - Based on the tree species, crown diameter, and other factors, a risk value is calculated to determine the likelihood of the tree contacting the power line. - If the risk value is high, a work order is issued to maintain the tree and prevent it from coming into contact with the power line.

Abstract

An embodiment includes identifying a tree type of vegetation depicted in an image. The embodiment segments that portion of the image using edge-detection processing resulting in a contour line that defines a tree perimeter. The embodiment detects that the tree is within a buffer distance from a power line. The embodiment determines the tree's species by comparing the contour line to candidate contour lines of different tree species and calculates a diameter of the tree's crown using the contour line. The embodiment estimates the tree's height using the species and the diameter of the crown. The embodiment calculates a risk value for the tree based on a risk of contact between the power line and the tree and issues a work order to maintain the tree to prevent contact with the power line.

LANGUAGE LEARNING THROUGH CONTENT TRANSLATION (17804642)

Main Inventor

Vinicius Maidana Alves

Brief explanation

- The patent application describes a method, computer program product, and computer system that facilitate learning a secondary language through content translation.

- The method involves identifying an educational corpus for the secondary language, which indicates words that have been learned in that language. - During playback of a multimedia file in the native language, a select portion of subtitles is determined, which includes native words corresponding to the learned words. - A modification is generated for the select portion, replacing the native words with the learned words in the subtitles. - The display of the multimedia file with subtitles is updated to visually represent the modification, such as by using a visual graphic to replace the native words. - The innovation aims to provide an engaging way for individuals to learn a secondary language by incorporating translated content into their native language media consumption.

Abstract

A method, a computer program product, and a computer system allow a secondary language to be learned through content translation in an engaged linguistical consumption format. The method includes determining an educational corpus for the secondary language that indicates learned words in the secondary language. The method includes determining a select portion of subtitles being shown during a play back of a multimedia file shown in a native language where the select portions include a native word corresponding to the learned words. The method includes generating a modification to the select portion such that the learned words replace the native word in the subtitles. A display of the play back of the multimedia file including the subtitles is updated with a visual graphic corresponding to the modification to replace the native word.

MECHANISM TO SHIFT THE HEAD SPAN OF A TAPE HEAD AT A WAFER LEVEL (18358684)

Main Inventor

Icko E.T. Iben

Brief explanation

The abstract describes a magnetic tape head, a magnetic tape drive, and a computational device.

• The magnetic tape head consists of multiple elements.
• The pitch (spacing) between adjacent elements is not the same.
• The invention is not specified further in the abstract.

Abstract

Provided are a magnetic tape head, a magnetic tape drive, and a computational device in which the magnetic tape head is comprised of a plurality of elements, wherein a pitch between adjacent elements of the plurality of elements is not identical.

ANGLED CONTACT WITH A NEGATIVE TAPERED PROFILE (17664671)

Main Inventor

Oleg Gluschenkov

Brief explanation

The patent application describes a microelectronics device with a specific design for the contact and gate regions. 

• The device has a contact located above the source/drain region, which is divided into three sections: bottom, middle, and top.
• The sidewalls of these sections are tapered towards the center Y-axis of the contact.
• There is also a gate contact located above the gate region, which also has tapered sidewalls towards the center Y-axis.
• The gate contact is positioned adjacent to the contact.
• The tapering of the sidewalls of the gate contact is the opposite of the tapering of the sidewalls of the contact.

Abstract

A microelectronics device including a gate region located adjacent to a source/drain region. A contact located above the source/drain region, where the contact has a bottom section, a middle section and top section, wherein the sidewalls of the bottom section, the middle section, and the top section of the contact are tapered towards a center Y-axis of the contact. A gate contact located above the gate region, where the gate contact has tapered sidewalls towards a center Y-axis of the gate contact. The gate contact is adjacent to the contact. The tapering of the sidewalls of the gate contact is inverse to the tapering of the sidewalls of the contact.

INTERCONNECT THROUGH GATE CUT FOR STACKED FET DEVICE (17664887)

Main Inventor

Ruilong Xie

Brief explanation

The patent application describes a microelectronic structure that consists of a stacked device region, which includes multiple top devices and multiple bottom devices. Each top device has a top source/drain, and each bottom device has a bottom source/drain. There is also a gate cut region adjacent to the stacked region, and an interconnect is present in the gate cut region. The interconnect is connected to at least two different devices within the stacked device region.

• The microelectronic structure includes a stacked device region with multiple top devices and multiple bottom devices.
• Each top device has a top source/drain, and each bottom device has a bottom source/drain.
• There is a gate cut region located next to the stacked region.
• An interconnect is present in the gate cut region.
• The interconnect is connected to at least two different devices within the stacked device region.

Abstract

A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.

METHOD AND STRUCTURE FOR FORMING LOW CONTACT RESISTANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (17664712)

Main Inventor

Ruilong Xie

Brief explanation

The abstract describes a CMOS device that includes a pFET epi and an nFET epi.

• The pFET epi has a single dielectric layer that wraps around a portion of the pFET epi and a confined trench epi on another portion of the pFET epi adjacent to a first contact.
• The nFET epi has a bi-layer dielectric liner that wraps around a portion of the nFET epi and another portion of the nFET epi adjacent to a second contact.

Abstract

A complementary metal oxide semiconductor (CMOS) device. The device includes a pFET epi and an nFET epi. The pFET epi includes a single dielectric layer that wraps around a first portion of the pFET epi and a confined trench epi on a second portion of the pFET epi that is adjacent a first contact. The nFET epi includes a bi-layer dielectric liner that wraps around a first portion of the nFET epi and a second portion of the nFET epi that is adjacent a second contact.

VTFET WITH BURIED POWER RAILS (18232510)

Main Inventor

Chen Zhang

Brief explanation

The patent application describes a semiconductor device that includes several components to improve its performance and functionality.

• The device includes a buried power rail, which is a layer that provides power to the device.
• A buried oxide (BOX) layer is formed on top of the buried power rail.
• A plurality of channel fins are formed on the BOX layer. These channel fins help control the flow of electrical current in the device.
• A bottom epitaxial layer is formed on the BOX layer and between the channel fins. This layer is electrically connected to the buried power rail.
• A gate stack is formed over the bottom epitaxial layer and contacts the channel fins. The gate stack includes a work function metal (WFM) layer and a high-x layer, which help control the flow of electrical current through the device.
• A top epitaxial layer is formed on top of the gate stack.

Overall, this semiconductor device design improves the electrical connectivity and performance of the device by utilizing a buried power rail, a buried oxide layer, and a gate stack with specific layers.

Abstract

A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

OPTIMIZATION FOR ACCESS POLICIES IN COMPUTER SYSTEMS (17826942)

Main Inventor

Shawn Patrick Authement

Brief explanation

- The patent application describes systems and methods for analyzing and optimizing access policies.

- The access policy optimization system analyzes access policies to reduce the overall number of policies. - A metric called access control health is computed to measure the current state of the access policies and determine if optimization is needed. - The access data, which includes access policies and access groups, is used for analysis. - A process called policy subgroup mapping is performed to identify subgroups of access policies. - Subgroups with a large number of entries are converted to access groups, users with those policies are added to the corresponding groups, and individual access policies are deleted. - Duplicative and redundant policies are identified and removed from the access data.

Abstract

Disclosed embodiments provide systems and methods for analyzing and optimizing access policies. Access policies are analyzed by an access policy optimization system. In cases where large numbers of users have similar access privileges, the number of overall policies can be significantly reduced. An access control health metric is computed on an original set of access data as a measure of the current state of the access policies. It can be used as an indication that optimization of the access policies is warranted. The access data can include access policies and/or access groups. A policy subgroup mapping process is performed to identify subgroups of access policies. Subgroups with a number of entries exceeding a predetermined value are converted to access groups, the users that have those policies are added to the corresponding access groups, and the individual access policies are deleted. Duplicative and/or redundant policies are identified and removed.

ELECTRICAL PORT LABELING (17664947)

Main Inventor

Bryan Edward Truong

Brief explanation

The patent application describes a method for displaying identification information for devices connected to multiple ports.

• The method involves determining which device is connected to a specific port.
• Communications are established between the device and the port using a transmitter and receiver.
• If identification information is available for the device, it is received from the transmitter and displayed on a display associated with the port.

Abstract

A method for displaying identification information for devices electrically coupled to a plurality of ports includes determining a first device is electrically coupled to a first port out of a plurality of ports. The method further includes establishing communications between a first communication transmitter on a first electrical connector for the first device and a first communication receiver associated with the first port. In response to determining first identification information is available for the first device, the method further includes receiving, from the first communication transmitter, at the first communication receiver the first identification information for the device. The method further includes displaying, in a first display, the first identification information for the first device, wherein the first display is associated with the first port.

MOTOR CONTROLLED RETRACTABLE EMC PROTECTION (18449096)

Main Inventor

John S. Werner

Brief explanation

The patent application describes a system and method for controlling an EMC (Electromagnetic Compatibility) protection apparatus in a removable component that is inserted into an end product.

• The removable component is inserted into the end product, which applies power to the EMC protection apparatus.
• The system detects whether a power good signal is present within the removable component.
• If a power good signal is detected, an EMC protection device is rotated from a retracted state to an engaged state.
• The EMC protection device is placed over an enclosure opening in the removable component, creating an EMC seal.
• The rotation of the EMC protection device may cause a delay in the full functionality of the removable component until the rotation is completed.

Abstract

A system and method for controlling an EMC protection apparatus in a removable component. The removable component is inserted into an end product. As a result of the insertion power is applied to the EMC protection apparatus. A determination is made as to whether a power good signal is detected within the removable component. In response to a power good signal, an EMC protection device is rotated from a retracted state to an engaged state such that the EMC protection device is placed over an enclosure opening in the removable component forming an EMC seal. Full functionality of the removable component can be delayed until such time as the rotation is completed.

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY WITH HEMISPHERICAL TOP ELECTRODE (17804795)

Main Inventor

Oscar van der Straten

Brief explanation

The patent application describes a memory device with a magnetic tunnel junction pillar and a sidewall spacer.

• The memory device includes a magnetic tunnel junction pillar and a sidewall spacer.
• The sidewall spacer is placed along the sidewalls of the magnetic tunnel junction pillar.
• The uppermost surface of the sidewall spacer is at the same level as the uppermost surface of the magnetic tunnel junction pillar.
• A dielectric hardmask made of an amorphous dielectric material is placed above a portion of the uppermost surface of the magnetic tunnel junction pillar.
• The dielectric hardmask has a hemispherical shape.
• A top electrode surrounds the dielectric hardmask and is located above the uppermost surface of the sidewall spacer.
• The top electrode also extends outwards from the dielectric hardmask and covers another portion of the uppermost surface of the magnetic tunnel junction pillar.

Abstract

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.